Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. |
| 3 | * Dave Liu <daveliu@freescale.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 11 | /* |
| 12 | * High Level Configuration Options |
| 13 | */ |
| 14 | #define CONFIG_E300 1 /* E300 family */ |
Peter Tyser | 72f2d39 | 2009-05-22 17:23:25 -0500 | [diff] [blame] | 15 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 16 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ |
| 17 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 18 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
| 19 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 20 | /* |
| 21 | * System Clock Setup |
| 22 | */ |
| 23 | #ifdef CONFIG_PCISLAVE |
| 24 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ |
| 25 | #else |
| 26 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
| 27 | #endif |
| 28 | |
| 29 | #ifndef CONFIG_SYS_CLK_FREQ |
| 30 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 31 | #endif |
| 32 | |
| 33 | /* |
| 34 | * Hardware Reset Configuration Word |
| 35 | * if CLKIN is 66MHz, then |
| 36 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz |
| 37 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | #define CONFIG_SYS_HRCW_LOW (\ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 39 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 40 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 41 | HRCWL_SVCOD_DIV_2 |\ |
| 42 | HRCWL_CSB_TO_CLKIN_6X1 |\ |
| 43 | HRCWL_CORE_TO_CSB_1_5X1) |
| 44 | |
| 45 | #ifdef CONFIG_PCISLAVE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_HRCW_HIGH (\ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 47 | HRCWH_PCI_AGENT |\ |
| 48 | HRCWH_PCI1_ARBITER_DISABLE |\ |
| 49 | HRCWH_CORE_ENABLE |\ |
| 50 | HRCWH_FROM_0XFFF00100 |\ |
| 51 | HRCWH_BOOTSEQ_DISABLE |\ |
| 52 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 53 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 54 | HRCWH_RL_EXT_LEGACY |\ |
| 55 | HRCWH_TSEC1M_IN_RGMII |\ |
| 56 | HRCWH_TSEC2M_IN_RGMII |\ |
| 57 | HRCWH_BIG_ENDIAN |\ |
| 58 | HRCWH_LDP_CLEAR) |
| 59 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 60 | #define CONFIG_SYS_HRCW_HIGH (\ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 61 | HRCWH_PCI_HOST |\ |
| 62 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 63 | HRCWH_CORE_ENABLE |\ |
| 64 | HRCWH_FROM_0X00000100 |\ |
| 65 | HRCWH_BOOTSEQ_DISABLE |\ |
| 66 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 67 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 68 | HRCWH_RL_EXT_LEGACY |\ |
| 69 | HRCWH_TSEC1M_IN_RGMII |\ |
| 70 | HRCWH_TSEC2M_IN_RGMII |\ |
| 71 | HRCWH_BIG_ENDIAN |\ |
| 72 | HRCWH_LDP_CLEAR) |
| 73 | #endif |
| 74 | |
Dave Liu | ed5a098 | 2008-03-04 16:59:22 +0800 | [diff] [blame] | 75 | /* Arbiter Configuration Register */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 77 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
Dave Liu | ed5a098 | 2008-03-04 16:59:22 +0800 | [diff] [blame] | 78 | |
| 79 | /* System Priority Control Register */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 80 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ |
Dave Liu | ed5a098 | 2008-03-04 16:59:22 +0800 | [diff] [blame] | 81 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 82 | /* |
Dave Liu | ed5a098 | 2008-03-04 16:59:22 +0800 | [diff] [blame] | 83 | * IP blocks clock configuration |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 84 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ |
| 86 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 87 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * System IO Config |
| 91 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_SICRH 0x00000000 |
| 93 | #define CONFIG_SYS_SICRL 0x00000000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 94 | |
| 95 | /* |
| 96 | * Output Buffer Impedance |
| 97 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 98 | #define CONFIG_SYS_OBIR 0x31100000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 99 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 100 | #define CONFIG_BOARD_EARLY_INIT_R |
Anton Vorontsov | 5cd6152 | 2009-06-10 00:25:31 +0400 | [diff] [blame] | 101 | #define CONFIG_HWCONFIG |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 102 | |
| 103 | /* |
| 104 | * IMMR new address |
| 105 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_IMMR 0xE0000000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * DDR Setup |
| 110 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
| 112 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 113 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 114 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
| 115 | #define CONFIG_SYS_83XX_DDR_USES_CS0 |
Joe Hershberger | cc03b80 | 2011-10-11 23:57:29 -0500 | [diff] [blame] | 116 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
| 117 | | DDRCDR_ODT \ |
| 118 | | DDRCDR_Q_DRN) |
| 119 | /* 0x80080001 */ /* ODT 150ohm on SoC */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 120 | |
| 121 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ |
| 122 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
| 123 | |
| 124 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 125 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ |
| 126 | |
| 127 | #if defined(CONFIG_SPD_EEPROM) |
| 128 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ |
| 129 | #else |
| 130 | /* |
| 131 | * Manually set up DDR parameters |
Dave Liu | 925c8c8 | 2008-01-10 23:07:23 +0800 | [diff] [blame] | 132 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 133 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
| 134 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
| 136 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 137 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
Joe Hershberger | cc03b80 | 2011-10-11 23:57:29 -0500 | [diff] [blame] | 138 | | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ |
| 139 | | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ |
| 140 | | CSCONFIG_ROW_BIT_14 \ |
| 141 | | CSCONFIG_COL_BIT_10) |
| 142 | /* 0x80010202 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 144 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
| 145 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
| 146 | | (0 << TIMING_CFG0_RRT_SHIFT) \ |
| 147 | | (0 << TIMING_CFG0_WWT_SHIFT) \ |
| 148 | | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ |
| 149 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ |
| 150 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ |
| 151 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 152 | /* 0x00620802 */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 153 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
| 154 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
| 155 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ |
| 156 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ |
| 157 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ |
| 158 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ |
| 159 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ |
| 160 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 161 | /* 0x3935d322 */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 162 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
| 163 | | (6 << TIMING_CFG2_CPO_SHIFT) \ |
| 164 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ |
| 165 | | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ |
| 166 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ |
| 167 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ |
| 168 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) |
Dave Liu | 925c8c8 | 2008-01-10 23:07:23 +0800 | [diff] [blame] | 169 | /* 0x131088c8 */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 170 | #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
| 171 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 172 | /* 0x03E00100 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
| 174 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 175 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
| 176 | | (0x1432 << SDRAM_MODE_SD_SHIFT)) |
Dave Liu | 925c8c8 | 2008-01-10 23:07:23 +0800 | [diff] [blame] | 177 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 178 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 179 | #endif |
| 180 | |
| 181 | /* |
| 182 | * Memory test |
| 183 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 185 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ |
| 186 | #define CONFIG_SYS_MEMTEST_END 0x00140000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 187 | |
| 188 | /* |
| 189 | * The reserved memory |
| 190 | */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 192 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 194 | #define CONFIG_SYS_RAMBOOT |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 195 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #undef CONFIG_SYS_RAMBOOT |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 197 | #endif |
| 198 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
Kevin Hao | 349a015 | 2016-07-08 11:25:14 +0800 | [diff] [blame] | 200 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 201 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 202 | |
| 203 | /* |
| 204 | * Initial RAM Base Address Setup |
| 205 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 207 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 208 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 209 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 210 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 211 | |
| 212 | /* |
| 213 | * Local Bus Configuration & Clock Setup |
| 214 | */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 215 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 216 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 217 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
Becky Bruce | dfe6e23 | 2010-06-17 11:37:18 -0500 | [diff] [blame] | 218 | #define CONFIG_FSL_ELBC 1 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 219 | |
| 220 | /* |
| 221 | * FLASH on the Local Bus |
| 222 | */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 223 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 224 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 225 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
| 226 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ |
| 227 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 228 | |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 229 | /* Window base at flash base */ |
| 230 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 231 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 232 | |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 233 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 234 | | BR_PS_16 /* 16 bit port */ \ |
| 235 | | BR_MS_GPCM /* MSEL = GPCM */ \ |
| 236 | | BR_V) /* valid */ |
| 237 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
Dave Liu | 723dff9 | 2008-01-10 23:08:26 +0800 | [diff] [blame] | 238 | | OR_UPM_XAM \ |
| 239 | | OR_GPCM_CSNT \ |
Anton Vorontsov | a6c0c07 | 2008-05-29 18:14:56 +0400 | [diff] [blame] | 240 | | OR_GPCM_ACS_DIV2 \ |
Dave Liu | 723dff9 | 2008-01-10 23:08:26 +0800 | [diff] [blame] | 241 | | OR_GPCM_XACS \ |
| 242 | | OR_GPCM_SCY_15 \ |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 243 | | OR_GPCM_TRLX_SET \ |
| 244 | | OR_GPCM_EHTR_SET \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 245 | | OR_GPCM_EAD) |
Dave Liu | 723dff9 | 2008-01-10 23:08:26 +0800 | [diff] [blame] | 246 | /* 0xFE000FF7 */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 247 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 248 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 249 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 250 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 252 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 253 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * BCSR on the Local Bus |
| 257 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 258 | #define CONFIG_SYS_BCSR 0xF8000000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 259 | /* Access window base at BCSR base */ |
| 260 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 261 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 262 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 263 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ |
| 264 | | BR_PS_8 \ |
| 265 | | BR_MS_GPCM \ |
| 266 | | BR_V) |
| 267 | /* 0xF8000801 */ |
| 268 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
| 269 | | OR_GPCM_XAM \ |
| 270 | | OR_GPCM_CSNT \ |
| 271 | | OR_GPCM_XACS \ |
| 272 | | OR_GPCM_SCY_15 \ |
| 273 | | OR_GPCM_TRLX_SET \ |
| 274 | | OR_GPCM_EHTR_SET \ |
| 275 | | OR_GPCM_EAD) |
| 276 | /* 0xFFFFE9F7 */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 277 | |
| 278 | /* |
| 279 | * NAND Flash on the Local Bus |
| 280 | */ |
Anton Vorontsov | c753879 | 2008-10-08 20:52:54 +0400 | [diff] [blame] | 281 | #define CONFIG_CMD_NAND 1 |
Anton Vorontsov | c753879 | 2008-10-08 20:52:54 +0400 | [diff] [blame] | 282 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 283 | #define CONFIG_NAND_FSL_ELBC 1 |
Anton Vorontsov | c753879 | 2008-10-08 20:52:54 +0400 | [diff] [blame] | 284 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 285 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 286 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 287 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 288 | | BR_PS_8 /* 8 bit port */ \ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 289 | | BR_MS_FCM /* MSEL = FCM */ \ |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 290 | | BR_V) /* valid */ |
| 291 | #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ |
Anton Vorontsov | c753879 | 2008-10-08 20:52:54 +0400 | [diff] [blame] | 292 | | OR_FCM_BCTLD \ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 293 | | OR_FCM_CST \ |
| 294 | | OR_FCM_CHT \ |
| 295 | | OR_FCM_SCY_1 \ |
Anton Vorontsov | c753879 | 2008-10-08 20:52:54 +0400 | [diff] [blame] | 296 | | OR_FCM_RST \ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 297 | | OR_FCM_TRLX \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 298 | | OR_FCM_EHTR) |
Anton Vorontsov | c753879 | 2008-10-08 20:52:54 +0400 | [diff] [blame] | 299 | /* 0xFFFF919E */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 300 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 302 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * Serial Port |
| 306 | */ |
| 307 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_NS16550_SERIAL |
| 309 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 310 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 311 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 312 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 313 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 314 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 316 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 317 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 318 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 319 | #define CONFIG_SYS_I2C |
| 320 | #define CONFIG_SYS_I2C_FSL |
| 321 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 322 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 323 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 324 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 325 | |
| 326 | /* |
| 327 | * Config on-board RTC |
| 328 | */ |
| 329 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 330 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 331 | |
| 332 | /* |
| 333 | * General PCI |
| 334 | * Addresses are mapped 1-1. |
| 335 | */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 336 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
| 337 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE |
| 338 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 339 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
| 340 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE |
| 341 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ |
| 342 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 |
| 343 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 |
| 344 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 345 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 346 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
| 347 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 |
| 348 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 349 | |
Anton Vorontsov | 62842ec | 2009-01-08 04:26:19 +0300 | [diff] [blame] | 350 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
| 351 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 |
| 352 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 |
| 353 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 |
| 354 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 |
| 355 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 |
| 356 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 |
| 357 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 |
| 358 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 |
| 359 | |
| 360 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 |
| 361 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 |
| 362 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 |
| 363 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 |
| 364 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 |
| 365 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 |
| 366 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 |
| 367 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 |
| 368 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 |
| 369 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 370 | #ifdef CONFIG_PCI |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 371 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Anton Vorontsov | 30c6992 | 2008-10-02 19:17:33 +0400 | [diff] [blame] | 372 | #ifndef __ASSEMBLY__ |
| 373 | extern int board_pci_host_broken(void); |
| 374 | #endif |
Kim Phillips | f138429 | 2009-07-23 14:09:38 -0500 | [diff] [blame] | 375 | #define CONFIG_PCIE |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 376 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ |
| 377 | |
Anton Vorontsov | 504867a | 2008-10-14 22:58:53 +0400 | [diff] [blame] | 378 | #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ |
Nikhil Badola | c4cff52 | 2014-10-20 16:31:01 +0530 | [diff] [blame] | 379 | #define CONFIG_USB_EHCI |
| 380 | #define CONFIG_USB_EHCI_FSL |
| 381 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
Anton Vorontsov | 504867a | 2008-10-14 22:58:53 +0400 | [diff] [blame] | 382 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 383 | #undef CONFIG_EEPRO100 |
| 384 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 385 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 386 | #endif /* CONFIG_PCI */ |
| 387 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 388 | /* |
| 389 | * TSEC |
| 390 | */ |
| 391 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 392 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 393 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 394 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 395 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * TSEC ethernet configuration |
| 399 | */ |
| 400 | #define CONFIG_MII 1 /* MII PHY management */ |
| 401 | #define CONFIG_TSEC1 1 |
| 402 | #define CONFIG_TSEC1_NAME "eTSEC0" |
| 403 | #define CONFIG_TSEC2 1 |
| 404 | #define CONFIG_TSEC2_NAME "eTSEC1" |
| 405 | #define TSEC1_PHY_ADDR 2 |
| 406 | #define TSEC2_PHY_ADDR 3 |
Anton Vorontsov | 32b1b70 | 2008-10-02 18:32:25 +0400 | [diff] [blame] | 407 | #define TSEC1_PHY_ADDR_SGMII 8 |
| 408 | #define TSEC2_PHY_ADDR_SGMII 4 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 409 | #define TSEC1_PHYIDX 0 |
| 410 | #define TSEC2_PHYIDX 0 |
| 411 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 412 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 413 | |
| 414 | /* Options are: TSEC[0-1] */ |
| 415 | #define CONFIG_ETHPRIME "eTSEC1" |
| 416 | |
Dave Liu | b8dc587 | 2008-03-26 22:56:36 +0800 | [diff] [blame] | 417 | /* SERDES */ |
| 418 | #define CONFIG_FSL_SERDES |
| 419 | #define CONFIG_FSL_SERDES1 0xe3000 |
| 420 | #define CONFIG_FSL_SERDES2 0xe3100 |
| 421 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 422 | /* |
Dave Liu | 4056d7a | 2008-03-26 22:57:19 +0800 | [diff] [blame] | 423 | * SATA |
| 424 | */ |
| 425 | #define CONFIG_LIBATA |
| 426 | #define CONFIG_FSL_SATA |
| 427 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 428 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
Dave Liu | 4056d7a | 2008-03-26 22:57:19 +0800 | [diff] [blame] | 429 | #define CONFIG_SATA1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 430 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 431 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
| 432 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
Dave Liu | 4056d7a | 2008-03-26 22:57:19 +0800 | [diff] [blame] | 433 | #define CONFIG_SATA2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 434 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 435 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
| 436 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
Dave Liu | 4056d7a | 2008-03-26 22:57:19 +0800 | [diff] [blame] | 437 | |
| 438 | #ifdef CONFIG_FSL_SATA |
| 439 | #define CONFIG_LBA48 |
| 440 | #define CONFIG_CMD_SATA |
Dave Liu | 4056d7a | 2008-03-26 22:57:19 +0800 | [diff] [blame] | 441 | #endif |
| 442 | |
| 443 | /* |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 444 | * Environment |
| 445 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 446 | #ifndef CONFIG_SYS_RAMBOOT |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 447 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 448 | #define CONFIG_ENV_ADDR \ |
| 449 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 450 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 451 | #define CONFIG_ENV_SIZE 0x2000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 452 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 68a8756 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 453 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 454 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 455 | #define CONFIG_ENV_SIZE 0x2000 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 456 | #endif |
| 457 | |
| 458 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 459 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 460 | |
| 461 | /* |
| 462 | * BOOTP options |
| 463 | */ |
| 464 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 465 | #define CONFIG_BOOTP_BOOTPATH |
| 466 | #define CONFIG_BOOTP_GATEWAY |
| 467 | #define CONFIG_BOOTP_HOSTNAME |
| 468 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 469 | /* |
| 470 | * Command line configuration. |
| 471 | */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 472 | #define CONFIG_CMD_DATE |
| 473 | |
| 474 | #if defined(CONFIG_PCI) |
| 475 | #define CONFIG_CMD_PCI |
| 476 | #endif |
| 477 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 478 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
Kim Phillips | 26c16d8 | 2010-04-15 17:36:05 -0500 | [diff] [blame] | 479 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 480 | |
| 481 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 482 | |
Andy Fleming | 1463b4b | 2008-10-30 16:50:14 -0500 | [diff] [blame] | 483 | #ifdef CONFIG_MMC |
| 484 | #define CONFIG_FSL_ESDHC |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 485 | #define CONFIG_FSL_ESDHC_PIN_MUX |
Andy Fleming | 1463b4b | 2008-10-30 16:50:14 -0500 | [diff] [blame] | 486 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
Andy Fleming | 1463b4b | 2008-10-30 16:50:14 -0500 | [diff] [blame] | 487 | #endif |
| 488 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 489 | /* |
| 490 | * Miscellaneous configurable options |
| 491 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 492 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 493 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 494 | |
| 495 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 496 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 497 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 498 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 499 | #endif |
| 500 | |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 501 | /* Print Buffer Size */ |
| 502 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 503 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 504 | /* Boot Argument Buffer Size */ |
| 505 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 506 | |
| 507 | /* |
| 508 | * For booting Linux, the board info and command line data |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 509 | * have to be in the first 256 MB of memory, since this is |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 510 | * the maximum mapped by the Linux kernel during initialization. |
| 511 | */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 512 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
Kevin Hao | 9c74796 | 2016-07-08 11:25:15 +0800 | [diff] [blame] | 513 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 514 | |
| 515 | /* |
| 516 | * Core HID Setup |
| 517 | */ |
Kim Phillips | f3c7cd9 | 2010-04-20 19:37:54 -0500 | [diff] [blame] | 518 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 519 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
| 520 | HID0_ENABLE_INSTRUCTION_CACHE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 521 | #define CONFIG_SYS_HID2 HID2_HBE |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 522 | |
| 523 | /* |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 524 | * MMU Setup |
| 525 | */ |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 526 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 527 | |
| 528 | /* DDR: cache cacheable */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 529 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
| 530 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 531 | |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 532 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 533 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 534 | | BATL_MEMCOHERENCE) |
| 535 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ |
| 536 | | BATU_BL_256M \ |
| 537 | | BATU_VS \ |
| 538 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 539 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
| 540 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 541 | |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 542 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 543 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 544 | | BATL_MEMCOHERENCE) |
| 545 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ |
| 546 | | BATU_BL_256M \ |
| 547 | | BATU_VS \ |
| 548 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 549 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
| 550 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 551 | |
| 552 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 553 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 554 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 555 | | BATL_CACHEINHIBIT \ |
| 556 | | BATL_GUARDEDSTORAGE) |
| 557 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ |
| 558 | | BATU_BL_8M \ |
| 559 | | BATU_VS \ |
| 560 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 561 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
| 562 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 563 | |
| 564 | /* BCSR: cache-inhibit and guarded */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 565 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 566 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 567 | | BATL_CACHEINHIBIT \ |
| 568 | | BATL_GUARDEDSTORAGE) |
| 569 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ |
| 570 | | BATU_BL_128K \ |
| 571 | | BATU_VS \ |
| 572 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 573 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
| 574 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 575 | |
| 576 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 577 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 578 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 579 | | BATL_MEMCOHERENCE) |
| 580 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ |
| 581 | | BATU_BL_32M \ |
| 582 | | BATU_VS \ |
| 583 | | BATU_VP) |
| 584 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 585 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 586 | | BATL_CACHEINHIBIT \ |
| 587 | | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 588 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 589 | |
| 590 | /* Stack in dcache: cacheable, no memory coherence */ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 591 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 592 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
| 593 | | BATU_BL_128K \ |
| 594 | | BATU_VS \ |
| 595 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 596 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
| 597 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 598 | |
| 599 | #ifdef CONFIG_PCI |
| 600 | /* PCI MEM space: cacheable */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 601 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 602 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 603 | | BATL_MEMCOHERENCE) |
| 604 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ |
| 605 | | BATU_BL_256M \ |
| 606 | | BATU_VS \ |
| 607 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 608 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
| 609 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 610 | /* PCI MMIO space: cache-inhibit and guarded */ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 611 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 612 | | BATL_PP_RW \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 613 | | BATL_CACHEINHIBIT \ |
| 614 | | BATL_GUARDEDSTORAGE) |
| 615 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ |
| 616 | | BATU_BL_256M \ |
| 617 | | BATU_VS \ |
| 618 | | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 619 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
| 620 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 621 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 622 | #define CONFIG_SYS_IBAT6L (0) |
| 623 | #define CONFIG_SYS_IBAT6U (0) |
| 624 | #define CONFIG_SYS_IBAT7L (0) |
| 625 | #define CONFIG_SYS_IBAT7U (0) |
| 626 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
| 627 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
| 628 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
| 629 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 630 | #endif |
| 631 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 632 | #if defined(CONFIG_CMD_KGDB) |
| 633 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 634 | #endif |
| 635 | |
| 636 | /* |
| 637 | * Environment Configuration |
| 638 | */ |
| 639 | |
| 640 | #define CONFIG_ENV_OVERWRITE |
| 641 | |
| 642 | #if defined(CONFIG_TSEC_ENET) |
| 643 | #define CONFIG_HAS_ETH0 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 644 | #define CONFIG_HAS_ETH1 |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 645 | #endif |
| 646 | |
Kim Phillips | fd3a3fc | 2009-08-21 16:34:38 -0500 | [diff] [blame] | 647 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 648 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 649 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 650 | |
| 651 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 652 | "netdev=eth0\0" \ |
| 653 | "consoledev=ttyS0\0" \ |
| 654 | "ramdiskaddr=1000000\0" \ |
| 655 | "ramdiskfile=ramfs.83xx\0" \ |
| 656 | "fdtaddr=780000\0" \ |
| 657 | "fdtfile=mpc8379_mds.dtb\0" \ |
| 658 | "" |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 659 | |
| 660 | #define CONFIG_NFSBOOTCOMMAND \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 661 | "setenv bootargs root=/dev/nfs rw " \ |
| 662 | "nfsroot=$serverip:$rootpath " \ |
| 663 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
| 664 | "$netdev:off " \ |
| 665 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 666 | "tftp $loadaddr $bootfile;" \ |
| 667 | "tftp $fdtaddr $fdtfile;" \ |
| 668 | "bootm $loadaddr - $fdtaddr" |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 669 | |
| 670 | #define CONFIG_RAMBOOTCOMMAND \ |
Joe Hershberger | 0f19340 | 2011-10-11 23:57:18 -0500 | [diff] [blame] | 671 | "setenv bootargs root=/dev/ram rw " \ |
| 672 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 673 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 674 | "tftp $loadaddr $bootfile;" \ |
| 675 | "tftp $fdtaddr $fdtfile;" \ |
| 676 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 677 | |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 678 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 679 | |
| 680 | #endif /* __CONFIG_H */ |