| Dinh Nguyen | d94e18e | 2019-04-23 16:55:03 -0500 | [diff] [blame^] | 1 | # |
| 2 | # Cache controllers | ||||
| 3 | # | ||||
| 4 | |||||
| 5 | menu "Cache Controller drivers" | ||||
| 6 | |||||
| 7 | config CACHE | ||||
| 8 | bool "Enable Driver Model for Cache controllers" | ||||
| 9 | depends on DM | ||||
| 10 | help | ||||
| 11 | Enable driver model for cache controllers that are found on | ||||
| 12 | most CPU's. Cache is memory that the CPU can access directly and | ||||
| 13 | is usually located on the same chip. This uclass can be used for | ||||
| 14 | configuring settings that be found from a device tree file. | ||||
| 15 | |||||
| 16 | endmenu | ||||