Parthiban Nallathambi | 5e9147d | 2019-04-18 00:04:09 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2015-2019 Variscite Ltd. |
| 4 | * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> |
| 5 | */ |
| 6 | |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 7 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 8 | #include <net.h> |
Parthiban Nallathambi | 5e9147d | 2019-04-18 00:04:09 +0200 | [diff] [blame] | 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/crm_regs.h> |
| 11 | #include <asm/arch/mx6-pins.h> |
| 12 | #include <asm/arch/sys_proto.h> |
| 13 | #include <asm/mach-imx/iomux-v3.h> |
| 14 | #include <asm/mach-imx/mxc_i2c.h> |
Yangbo Lu | 7334038 | 2019-06-21 11:42:28 +0800 | [diff] [blame] | 15 | #include <fsl_esdhc_imx.h> |
Parthiban Nallathambi | 5e9147d | 2019-04-18 00:04:09 +0200 | [diff] [blame] | 16 | #include <linux/bitops.h> |
| 17 | #include <miiphy.h> |
| 18 | #include <netdev.h> |
| 19 | #include <usb.h> |
| 20 | #include <usb/ehci-ci.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | int dram_init(void) |
| 25 | { |
| 26 | gd->ram_size = imx_ddr_size(); |
| 27 | |
| 28 | return 0; |
| 29 | } |
| 30 | |
| 31 | #ifdef CONFIG_NAND_MXS |
| 32 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| 33 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| 34 | PAD_CTL_SRE_FAST) |
| 35 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| 36 | static iomux_v3_cfg_t const nand_pads[] = { |
| 37 | MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 38 | MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 39 | MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 40 | MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 41 | MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 42 | MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 43 | MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 44 | MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 45 | MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 46 | MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 47 | MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 48 | MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 49 | MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 50 | MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 51 | MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 52 | MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| 53 | }; |
| 54 | |
| 55 | static void setup_gpmi_nand(void) |
| 56 | { |
| 57 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 58 | |
| 59 | /* config gpmi nand iomux */ |
| 60 | imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); |
| 61 | |
| 62 | clrbits_le32(&mxc_ccm->CCGR4, |
| 63 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| 64 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| 65 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| 66 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| 67 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| 68 | |
| 69 | /* |
| 70 | * config gpmi and bch clock to 100 MHz |
| 71 | * bch/gpmi select PLL2 PFD2 400M |
| 72 | * 100M = 400M / 4 |
| 73 | */ |
| 74 | clrbits_le32(&mxc_ccm->cscmr1, |
| 75 | MXC_CCM_CSCMR1_BCH_CLK_SEL | |
| 76 | MXC_CCM_CSCMR1_GPMI_CLK_SEL); |
| 77 | clrsetbits_le32(&mxc_ccm->cscdr1, |
| 78 | MXC_CCM_CSCDR1_BCH_PODF_MASK | |
| 79 | MXC_CCM_CSCDR1_GPMI_PODF_MASK, |
| 80 | (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | |
| 81 | (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); |
| 82 | |
| 83 | /* enable gpmi and bch clock gating */ |
| 84 | setbits_le32(&mxc_ccm->CCGR4, |
| 85 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| 86 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| 87 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| 88 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| 89 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| 90 | |
| 91 | /* enable apbh clock gating */ |
| 92 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| 93 | } |
| 94 | #endif |
| 95 | |
| 96 | #ifdef CONFIG_FEC_MXC |
| 97 | #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 98 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| 99 | PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ |
| 100 | PAD_CTL_SRE_FAST) |
| 101 | #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| 102 | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ |
| 103 | PAD_CTL_ODE) |
| 104 | /* |
| 105 | * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only |
| 106 | * be used for ENET1 or ENET2, cannot be used for both. |
| 107 | */ |
| 108 | static iomux_v3_cfg_t const fec1_pads[] = { |
| 109 | MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), |
| 110 | MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 111 | MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 112 | MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 113 | MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 114 | MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), |
| 115 | MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 116 | MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 117 | MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 118 | MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 119 | }; |
| 120 | |
| 121 | static iomux_v3_cfg_t const fec2_pads[] = { |
| 122 | MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), |
| 123 | MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 124 | MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 125 | MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 126 | MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 127 | MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), |
| 128 | MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 129 | MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 130 | MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 131 | MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 132 | }; |
| 133 | |
| 134 | static void setup_iomux_fec(int fec_id) |
| 135 | { |
| 136 | if (fec_id == 0) |
| 137 | imx_iomux_v3_setup_multiple_pads(fec1_pads, |
| 138 | ARRAY_SIZE(fec1_pads)); |
| 139 | else |
| 140 | imx_iomux_v3_setup_multiple_pads(fec2_pads, |
| 141 | ARRAY_SIZE(fec2_pads)); |
| 142 | } |
| 143 | |
| 144 | int board_eth_init(bd_t *bis) |
| 145 | { |
| 146 | int ret = 0; |
| 147 | |
| 148 | ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, |
| 149 | CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
| 150 | |
| 151 | #if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER) |
| 152 | /* USB Ethernet Gadget */ |
| 153 | usb_eth_initialize(bis); |
| 154 | #endif |
| 155 | return ret; |
| 156 | } |
| 157 | |
| 158 | static int setup_fec(int fec_id) |
| 159 | { |
| 160 | struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 161 | int ret; |
| 162 | |
| 163 | if (fec_id == 0) { |
| 164 | /* |
| 165 | * Use 50M anatop loopback REF_CLK1 for ENET1, |
| 166 | * clear gpr1[13], set gpr1[17]. |
| 167 | */ |
| 168 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, |
| 169 | IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); |
| 170 | } else { |
| 171 | /* |
| 172 | * Use 50M anatop loopback REF_CLK2 for ENET2, |
| 173 | * clear gpr1[14], set gpr1[18]. |
| 174 | */ |
| 175 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, |
| 176 | IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); |
| 177 | } |
| 178 | |
| 179 | ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); |
| 180 | if (ret) |
| 181 | return ret; |
| 182 | |
| 183 | enable_enet_clk(1); |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | int board_phy_config(struct phy_device *phydev) |
| 189 | { |
| 190 | /* |
| 191 | * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select |
| 192 | * 50 MHz RMII clock mode. |
| 193 | */ |
| 194 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); |
| 195 | |
| 196 | if (phydev->drv->config) |
| 197 | phydev->drv->config(phydev); |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | #endif /* CONFIG_FEC_MXC */ |
| 202 | |
| 203 | int board_early_init_f(void) |
| 204 | { |
| 205 | setup_iomux_fec(CONFIG_FEC_ENET_DEV); |
| 206 | |
| 207 | return 0; |
| 208 | } |
| 209 | |
| 210 | int board_init(void) |
| 211 | { |
| 212 | /* Address of boot parameters */ |
| 213 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 214 | |
| 215 | #ifdef CONFIG_FEC_MXC |
| 216 | setup_fec(CONFIG_FEC_ENET_DEV); |
| 217 | #endif |
| 218 | |
| 219 | #ifdef CONFIG_NAND_MXS |
| 220 | setup_gpmi_nand(); |
| 221 | #endif |
| 222 | return 0; |
| 223 | } |
| 224 | |
| 225 | int checkboard(void) |
| 226 | { |
| 227 | puts("Board: Variscite DART-6UL Evaluation Kit\n"); |
| 228 | |
| 229 | return 0; |
| 230 | } |