| Tien Fong Chee | d938c81 | 2024-08-14 15:56:25 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2024 Intel Corporation <www.intel.com> |
| 4 | * Copyright (C) 2025 Altera Corporation <www.altera.com> |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #include <init.h> |
| 9 | #include <asm/global_data.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <hang.h> |
| 12 | #include <spl.h> |
| 13 | #include <asm/arch/base_addr_soc64.h> |
| 14 | #include <asm/arch/clock_manager.h> |
| 15 | #include <asm/arch/mailbox_s10.h> |
| 16 | #include <asm/arch/misc.h> |
| 17 | #include <asm/arch/reset_manager.h> |
| 18 | #include <asm/arch/system_manager.h> |
| 19 | #include <wdt.h> |
| 20 | #include <dm/uclass.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | void board_init_f(ulong dummy) |
| 25 | { |
| 26 | int ret; |
| 27 | struct udevice *dev; |
| 28 | |
| 29 | ret = spl_early_init(); |
| 30 | if (ret) |
| 31 | hang(); |
| 32 | |
| 33 | socfpga_get_sys_mgr_addr("sysmgr@10d12000"); |
| 34 | socfpga_get_managers_addr(); |
| 35 | |
| 36 | sysmgr_pinmux_init(); |
| 37 | |
| 38 | /* Ensure watchdog is paused when debugging is happening */ |
| 39 | writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, |
| 40 | socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); |
| 41 | |
| 42 | timer_init(); |
| 43 | |
| 44 | ret = uclass_get_device(UCLASS_CLK, 0, &dev); |
| 45 | if (ret) { |
| 46 | debug("Clock init failed: %d\n", ret); |
| 47 | hang(); |
| 48 | } |
| 49 | |
| 50 | /* |
| 51 | * Enable watchdog as early as possible before initializing other |
| 52 | * component. Watchdog need to be enabled after clock driver because |
| 53 | * it will retrieve the clock frequency from clock driver. |
| 54 | */ |
| 55 | if (CONFIG_IS_ENABLED(WDT)) |
| 56 | initr_watchdog(); |
| 57 | |
| 58 | preloader_console_init(); |
| 59 | print_reset_info(); |
| 60 | cm_print_clock_quick_summary(); |
| 61 | |
| 62 | ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev); |
| 63 | if (ret) { |
| 64 | printf("HPS CCU settings init failed: %d\n", ret); |
| 65 | hang(); |
| 66 | } |
| 67 | |
| 68 | ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev); |
| 69 | if (ret) { |
| 70 | printf("HPS firewall settings init failed: %d\n", ret); |
| 71 | hang(); |
| 72 | } |
| 73 | |
| 74 | if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { |
| 75 | ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
| 76 | if (ret) { |
| 77 | debug("DRAM init failed: %d\n", ret); |
| 78 | hang(); |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | mbox_init(); |
| 83 | |
| 84 | if (IS_ENABLED(CONFIG_CADENCE_QSPI)) |
| 85 | mbox_qspi_open(); |
| 86 | |
| 87 | /* Enable non secure access to ocram */ |
| 88 | clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0)); |
| 89 | } |