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git01.mediatek.com / filogic / uboot / d8e69e0fa036fd3e3f5d6895f6d75bf3872b80a7 / . / board / ip860 / u-boot.lds.debug
blob: e561bb4824ce7a0a84d8223978f74a75c2292eeb [file] [log] [blame]
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]6 */
7
8OUTPUT_ARCH(powerpc)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]9/* Do we need any of these for elf?
10 __DYNAMIC = 0; */
11SECTIONS
12{
13 /* Read-only sections, merged into text segment: */
14 . = + SIZEOF_HEADERS;
15 .interp : { *(.interp) }
16 .hash : { *(.hash) }
17 .dynsym : { *(.dynsym) }
18 .dynstr : { *(.dynstr) }
19 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]20 .rela.text : { *(.rela.text) }
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]21 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]22 .rela.data : { *(.rela.data) }
23 .rel.rodata : { *(.rel.rodata) }
24 .rela.rodata : { *(.rela.rodata) }
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]25 .rel.got : { *(.rel.got) }
26 .rela.got : { *(.rela.got) }
27 .rel.ctors : { *(.rel.ctors) }
28 .rela.ctors : { *(.rela.ctors) }
29 .rel.dtors : { *(.rel.dtors) }
30 .rela.dtors : { *(.rela.dtors) }
31 .rel.bss : { *(.rel.bss) }
32 .rela.bss : { *(.rela.bss) }
33 .rel.plt : { *(.rel.plt) }
34 .rela.plt : { *(.rela.plt) }
35 .init : { *(.init) }
36 .plt : { *(.plt) }
37 .text :
38 {
39 /* WARNING - the following is hand-optimized to fit within */
40 /* the sector layout of our flash chips! XXX FIXME XXX */
41
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]42 arch/powerpc/cpu/mpc8xx/start.o (.text)
43 arch/powerpc/lib/ppcstring.o (.text)
44 arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
45 arch/powerpc/lib/time.o (.text)
46 arch/powerpc/lib/ticks.o (.text)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]47/**
48 . = env_offset;
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]49 common/env_embedded.o(.text)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]50**/
51 *(.text)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]52 *(.got1)
53 }
54 _etext = .;
55 PROVIDE (etext = .);
56 .rodata :
57 {
58 *(.rodata)
59 *(.rodata1)
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]60 *(.rodata.str1.4)
61 *(.eh_frame)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]62 }
63 .fini : { *(.fini) } =0
64 .ctors : { *(.ctors) }
65 .dtors : { *(.dtors) }
66
67 /* Read-write section, merged into data segment: */
68 . = (. + 0x0FFF) & 0xFFFFF000;
69 _erotext = .;
70 PROVIDE (erotext = .);
71 .reloc :
72 {
73 *(.got)
74 _GOT2_TABLE_ = .;
75 *(.got2)
76 _FIXUP_TABLE_ = .;
77 *(.fixup)
78 }
79 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
80 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
81
82 .data :
83 {
84 *(.data)
85 *(.data1)
86 *(.sdata)
87 *(.sdata2)
88 *(.dynamic)
89 CONSTRUCTORS
90 }
91 _edata = .;
92 PROVIDE (edata = .);
93
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]94
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]95 . = ALIGN(4);
96 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]97 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]98 }
99
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]100
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]101 __start___ex_table = .;
102 __ex_table : { *(__ex_table) }
103 __stop___ex_table = .;
104
105 . = ALIGN(4096);
106 __init_begin = .;
107 .text.init : { *(.text.init) }
108 .data.init : { *(.data.init) }
109 . = ALIGN(4096);
110 __init_end = .;
111
112 __bss_start = .;
113 .bss :
114 {
115 *(.sbss) *(.scommon)
116 *(.dynbss)
117 *(.bss)
118 *(COMMON)
119 }
Albert ARIBAUD0198f9d2013-03-30 00:19:53 +0000[diff] [blame]120 __bss_end = . ;
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]121 PROVIDE (end = .);
122}