blob: cf2efdbe230b04b52b712a8f3c976b25e9ccb91d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -07002/**
3 * (C) Copyright 2014, Cavium Inc.
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -07004**/
5
6#ifndef __THUNDERX_88XX_H__
7#define __THUNDERX_88XX_H__
8
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -07009#define MEM_BASE 0x00500000
10
Sergey Temerkhanov62dce242015-10-14 09:55:51 -070011#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
12
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070013/* Link Definitions */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070014
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070015/* SMP Spin Table Definitions */
16#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
17
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070018/* PL011 Serial Configuration */
19
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070020#define CONFIG_PL011_CLOCK 24000000
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070021
22/* Generic Interrupt Controller Definitions */
23#define GICD_BASE (0x801000000000)
24#define GICR_BASE (0x801000002000)
25#define CONFIG_SYS_SERIAL0 0x87e024000000
26#define CONFIG_SYS_SERIAL1 0x87e025000000
27
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070028/* Miscellaneous configurable options */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070029
30/* Physical Memory Map */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070031#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
32#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
33#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
34
35/* Initial environment variables */
36#define UBOOT_IMG_HEAD_SIZE 0x40
37/* C80000 - 0x40 */
38#define CONFIG_EXTRA_ENV_SETTINGS \
39 "kernel_addr=08007ffc0\0" \
40 "fdt_addr=0x94C00000\0" \
41 "fdt_high=0x9fffffff\0"
42
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070043/* Do not preserve environment */
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070044
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070045#define PLL_REF_CLK 50000000 /* 50 MHz */
46#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
47
48#endif /* __THUNDERX_88XX_H__ */