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git01.mediatek.com / filogic / uboot / d8b34fb9187e679b32302105f206525f5e2b26a7 / . / include / configs / at91sam9261ek.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]2/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +0100[diff] [blame]4 * Stelian Pop <stelian@popies.net>
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9261EK board.
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* ARM asynchronous clock */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]14#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich443873d2010-02-24 10:29:16 +0100[diff] [blame]15#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]16
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]17#include <asm/hardware.h>
18
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]19/*
20 * Hardware drivers
21 */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]22
Stelian Pop905ed222008-05-08 14:52:30 +0200[diff] [blame]23/* LCD */
Stelian Pop905ed222008-05-08 14:52:30 +0200[diff] [blame]24#define LCD_BPP LCD_COLOR8
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]25
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]26/* SDRAM */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]27#define CONFIG_SYS_SDRAM_BASE 0x20000000
28#define CONFIG_SYS_SDRAM_SIZE 0x04000000
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]29#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
30#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]31
32/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]33#ifdef CONFIG_CMD_NAND
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]34#define CONFIG_SYS_MAX_NAND_DEVICE 1
35#define CONFIG_SYS_NAND_BASE 0x40000000
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]36#define CONFIG_SYS_NAND_DBW_8
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]37/* our ALE is AD22 */
38#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
39/* our CLE is AD21 */
40#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
41#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
42#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
Wolfgang Denk1f797742009-07-18 21:52:24 +0200[diff] [blame]43
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]44#endif
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]45
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]46/* Ethernet */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]47#define CONFIG_DM9000_BASE 0x30000000
48#define DM9000_IO CONFIG_DM9000_BASE
49#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]50#define CONFIG_DM9000_USE_16BIT
51#define CONFIG_DM9000_NO_SROM
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]52
53/* USB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]54#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]55
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]56#endif