blob: 15e82de2fe184d79684fbc329f1a3b1216527739 [file] [log] [blame]
Simon Glassddb39b22019-08-24 14:10:32 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
7#include <handoff.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glassddb39b22019-08-24 14:10:32 -06009#include <asm/fsp/fsp_support.h>
10#include <asm/e820.h>
11#include <asm/mrccache.h>
Simon Glass8ccadee2019-12-06 21:42:12 -070012#include <asm/mtrr.h>
Simon Glassddb39b22019-08-24 14:10:32 -060013#include <asm/post.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17int fsp_scan_for_ram_size(void)
18{
19 phys_size_t ram_size = 0;
20 const struct hob_header *hdr;
21 struct hob_res_desc *res_desc;
22
23 hdr = gd->arch.hob_list;
24 while (!end_of_hob(hdr)) {
25 if (hdr->type == HOB_TYPE_RES_DESC) {
26 res_desc = (struct hob_res_desc *)hdr;
27 if (res_desc->type == RES_SYS_MEM ||
28 res_desc->type == RES_MEM_RESERVED)
29 ram_size += res_desc->len;
30 }
31 hdr = get_next_hob(hdr);
32 }
33
34 gd->ram_size = ram_size;
35 post_code(POST_DRAM);
36
37 return 0;
38};
39
40int dram_init_banksize(void)
41{
Simon Glass75545f72019-12-06 21:42:11 -070042 const struct hob_header *hdr;
43 struct hob_res_desc *res_desc;
44 phys_addr_t low_end;
45 uint bank;
46
Simon Glassd89c4a32020-04-26 09:12:53 -060047 if (!ll_boot_init()) {
48 gd->bd->bi_dram[0].start = 0;
49 gd->bd->bi_dram[0].size = gd->ram_size;
50
51 mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
52 return 0;
53 }
54
Simon Glass75545f72019-12-06 21:42:11 -070055 low_end = 0;
56 for (bank = 1, hdr = gd->arch.hob_list;
57 bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
58 hdr = get_next_hob(hdr)) {
59 if (hdr->type != HOB_TYPE_RES_DESC)
60 continue;
61 res_desc = (struct hob_res_desc *)hdr;
62 if (res_desc->type != RES_SYS_MEM &&
63 res_desc->type != RES_MEM_RESERVED)
64 continue;
65 if (res_desc->phys_start < (1ULL << 32)) {
66 low_end = max(low_end,
67 res_desc->phys_start + res_desc->len);
68 continue;
69 }
70
71 gd->bd->bi_dram[bank].start = res_desc->phys_start;
72 gd->bd->bi_dram[bank].size = res_desc->len;
Simon Glass8ccadee2019-12-06 21:42:12 -070073 mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
74 res_desc->len);
Simon Glass75545f72019-12-06 21:42:11 -070075 log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
76 gd->bd->bi_dram[bank].size);
77 }
78
79 /* Add the memory below 4GB */
Simon Glassddb39b22019-08-24 14:10:32 -060080 gd->bd->bi_dram[0].start = 0;
Simon Glass75545f72019-12-06 21:42:11 -070081 gd->bd->bi_dram[0].size = low_end;
Simon Glassddb39b22019-08-24 14:10:32 -060082
Simon Glass8ccadee2019-12-06 21:42:12 -070083 mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
84
Simon Glassddb39b22019-08-24 14:10:32 -060085 return 0;
86}
87
88unsigned int install_e820_map(unsigned int max_entries,
89 struct e820_entry *entries)
90{
91 unsigned int num_entries = 0;
92 const struct hob_header *hdr;
93 struct hob_res_desc *res_desc;
94
95 hdr = gd->arch.hob_list;
96
97 while (!end_of_hob(hdr)) {
98 if (hdr->type == HOB_TYPE_RES_DESC) {
99 res_desc = (struct hob_res_desc *)hdr;
100 entries[num_entries].addr = res_desc->phys_start;
101 entries[num_entries].size = res_desc->len;
102
103 if (res_desc->type == RES_SYS_MEM)
104 entries[num_entries].type = E820_RAM;
105 else if (res_desc->type == RES_MEM_RESERVED)
106 entries[num_entries].type = E820_RESERVED;
107
108 num_entries++;
109 }
110 hdr = get_next_hob(hdr);
111 }
112
113 /* Mark PCIe ECAM address range as reserved */
114 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
115 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
116 entries[num_entries].type = E820_RESERVED;
117 num_entries++;
118
119#ifdef CONFIG_HAVE_ACPI_RESUME
120 /*
121 * Everything between U-Boot's stack and ram top needs to be
122 * reserved in order for ACPI S3 resume to work.
123 */
124 entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
125 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
126 CONFIG_STACK_SIZE;
127 entries[num_entries].type = E820_RESERVED;
128 num_entries++;
129#endif
130
131 return num_entries;
132}
Simon Glass25628082019-09-25 08:11:41 -0600133
134#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
135int handoff_arch_save(struct spl_handoff *ho)
136{
137 ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
138 ho->arch.hob_list = gd->arch.hob_list;
139
140 return 0;
141}
142#endif