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Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +02001#ifndef __ASM_ARM_SYSTEM_H
2#define __ASM_ARM_SYSTEM_H
3
David Feng85fd5f12013-12-14 11:47:35 +08004#ifdef CONFIG_ARM64
5
6/*
7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
8 */
9#define CR_M (1 << 0) /* MMU enable */
10#define CR_A (1 << 1) /* Alignment abort enable */
11#define CR_C (1 << 2) /* Dcache enable */
12#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
13#define CR_I (1 << 12) /* Icache enable */
14#define CR_WXN (1 << 19) /* Write Permision Imply XN */
15#define CR_EE (1 << 25) /* Exception (Big) Endian */
16
17#define PGTABLE_SIZE (0x10000)
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +053018/* 2MB granularity */
19#define MMU_SECTION_SHIFT 21
David Feng85fd5f12013-12-14 11:47:35 +080020
21#ifndef __ASSEMBLY__
22
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +053023enum dcache_option {
24 DCACHE_OFF = 0x3,
25};
26
David Feng85fd5f12013-12-14 11:47:35 +080027#define isb() \
28 ({asm volatile( \
29 "isb" : : : "memory"); \
30 })
31
32#define wfi() \
33 ({asm volatile( \
34 "wfi" : : : "memory"); \
35 })
36
37static inline unsigned int current_el(void)
38{
39 unsigned int el;
40 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
41 return el >> 2;
42}
43
44static inline unsigned int get_sctlr(void)
45{
46 unsigned int el, val;
47
48 el = current_el();
49 if (el == 1)
50 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
51 else if (el == 2)
52 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
53 else
54 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
55
56 return val;
57}
58
59static inline void set_sctlr(unsigned int val)
60{
61 unsigned int el;
62
63 el = current_el();
64 if (el == 1)
65 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
66 else if (el == 2)
67 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
68 else
69 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
70
71 asm volatile("isb");
72}
73
74void __asm_flush_dcache_all(void);
York Sunef042012014-02-26 13:26:04 -080075void __asm_invalidate_dcache_all(void);
David Feng85fd5f12013-12-14 11:47:35 +080076void __asm_flush_dcache_range(u64 start, u64 end);
77void __asm_invalidate_tlb_all(void);
78void __asm_invalidate_icache_all(void);
York Sun1ce575f2015-01-06 13:18:42 -080079int __asm_flush_l3_cache(void);
David Feng85fd5f12013-12-14 11:47:35 +080080
81void armv8_switch_to_el2(void);
82void armv8_switch_to_el1(void);
83void gic_init(void);
84void gic_send_sgi(unsigned long sgino);
85void wait_for_wakeup(void);
Ian Campbelld07e7b02015-04-21 07:18:36 +020086void protect_secure_region(void);
David Feng85fd5f12013-12-14 11:47:35 +080087void smp_kick_all_cpus(void);
88
York Suna84cd722014-06-23 15:15:54 -070089void flush_l3_cache(void);
90
David Feng85fd5f12013-12-14 11:47:35 +080091#endif /* __ASSEMBLY__ */
92
93#else /* CONFIG_ARM64 */
94
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020095#ifdef __KERNEL__
96
97#define CPU_ARCH_UNKNOWN 0
98#define CPU_ARCH_ARMv3 1
99#define CPU_ARCH_ARMv4 2
100#define CPU_ARCH_ARMv4T 3
101#define CPU_ARCH_ARMv5 4
102#define CPU_ARCH_ARMv5T 5
103#define CPU_ARCH_ARMv5TE 6
104#define CPU_ARCH_ARMv5TEJ 7
105#define CPU_ARCH_ARMv6 8
106#define CPU_ARCH_ARMv7 9
107
108/*
109 * CR1 bits (CP#15 CR1)
110 */
111#define CR_M (1 << 0) /* MMU enable */
112#define CR_A (1 << 1) /* Alignment abort enable */
113#define CR_C (1 << 2) /* Dcache enable */
114#define CR_W (1 << 3) /* Write buffer enable */
115#define CR_P (1 << 4) /* 32-bit exception handler */
116#define CR_D (1 << 5) /* 32-bit data address range */
117#define CR_L (1 << 6) /* Implementation defined */
118#define CR_B (1 << 7) /* Big endian */
119#define CR_S (1 << 8) /* System MMU protection */
120#define CR_R (1 << 9) /* ROM MMU protection */
121#define CR_F (1 << 10) /* Implementation defined */
122#define CR_Z (1 << 11) /* Implementation defined */
123#define CR_I (1 << 12) /* Icache enable */
124#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
125#define CR_RR (1 << 14) /* Round Robin cache replacement */
126#define CR_L4 (1 << 15) /* LDR pc can set T bit */
127#define CR_DT (1 << 16)
128#define CR_IT (1 << 18)
129#define CR_ST (1 << 19)
130#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
131#define CR_U (1 << 22) /* Unaligned access operation */
132#define CR_XP (1 << 23) /* Extended page tables */
133#define CR_VE (1 << 24) /* Vectored interrupts */
134#define CR_EE (1 << 25) /* Exception (Big) Endian */
135#define CR_TRE (1 << 28) /* TEX remap enable */
136#define CR_AFE (1 << 29) /* Access flag enable */
137#define CR_TE (1 << 30) /* Thumb exception enable */
138
David Feng85fd5f12013-12-14 11:47:35 +0800139#define PGTABLE_SIZE (4096 * 4)
140
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200141/*
142 * This is used to ensure the compiler did actually allocate the register we
143 * asked it for some inline assembly sequences. Apparently we can't trust
144 * the compiler from one version to another so a bit of paranoia won't hurt.
145 * This string is meant to be concatenated with the inline asm string and
146 * will cause compilation to stop on mismatch.
147 * (for details, see gcc PR 15089)
148 */
149#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
150
151#ifndef __ASSEMBLY__
152
Simon Glass47197fe2015-02-07 10:47:28 -0700153/**
154 * save_boot_params() - Save boot parameters before starting reset sequence
155 *
156 * If you provide this function it will be called immediately U-Boot starts,
157 * both for SPL and U-Boot proper.
158 *
159 * All registers are unchanged from U-Boot entry. No registers need be
160 * preserved.
161 *
162 * This is not a normal C function. There is no stack. Return by branching to
163 * save_boot_params_ret.
164 *
165 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
166 */
167
Simon Glass32db57d2015-05-04 11:31:03 -0600168/**
169 * save_boot_params_ret() - Return from save_boot_params()
170 *
171 * If you provide save_boot_params(), then you should jump back to this
172 * function when done. Try to preserve all registers.
173 *
174 * If your implementation of save_boot_params() is in C then it is acceptable
175 * to simply call save_boot_params_ret() at the end of your function. Since
176 * there is no link register set up, you cannot just exit the function. U-Boot
177 * will return to the (initialised) value of lr, and likely crash/hang.
178 *
179 * If your implementation of save_boot_params() is in assembler then you
180 * should use 'b' or 'bx' to return to save_boot_params_ret.
181 */
182void save_boot_params_ret(void);
183
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200184#define isb() __asm__ __volatile__ ("" : : : "memory")
185
186#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
187
Rob Herringaa470302012-12-02 17:06:21 +0000188#ifdef __ARM_ARCH_7A__
189#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
190#else
191#define wfi()
192#endif
193
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200194static inline unsigned int get_cr(void)
195{
196 unsigned int val;
197 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
198 return val;
199}
200
201static inline void set_cr(unsigned int val)
202{
203 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
204 : : "r" (val) : "cc");
205 isb();
206}
207
R Sricharan06396c12013-03-04 20:04:45 +0000208static inline unsigned int get_dacr(void)
209{
210 unsigned int val;
211 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
212 return val;
213}
214
215static inline void set_dacr(unsigned int val)
216{
217 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
218 : : "r" (val) : "cc");
219 isb();
220}
221
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500222#ifdef CONFIG_ARMV7
223/* Short-Descriptor Translation Table Level 1 Bits */
224#define TTB_SECT_NS_MASK (1 << 19)
225#define TTB_SECT_NG_MASK (1 << 17)
226#define TTB_SECT_S_MASK (1 << 16)
227/* Note: TTB AP bits are set elsewhere */
228#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
229#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
230#define TTB_SECT_XN_MASK (1 << 4)
231#define TTB_SECT_C_MASK (1 << 3)
232#define TTB_SECT_B_MASK (1 << 2)
233#define TTB_SECT (2 << 0)
234
Simon Glassa4f20792012-10-17 13:24:53 +0000235/* options available for data cache on each page */
236enum dcache_option {
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500237 DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
238 TTB_SECT_XN_MASK | TTB_SECT,
239 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
240 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
241 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
242};
243#else
244/* options available for data cache on each page */
245enum dcache_option {
Simon Glassa4f20792012-10-17 13:24:53 +0000246 DCACHE_OFF = 0x12,
247 DCACHE_WRITETHROUGH = 0x1a,
248 DCACHE_WRITEBACK = 0x1e,
Marek Vasut79b90722014-09-15 02:44:36 +0200249 DCACHE_WRITEALLOC = 0x16,
Simon Glassa4f20792012-10-17 13:24:53 +0000250};
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500251#endif
Simon Glassa4f20792012-10-17 13:24:53 +0000252
253/* Size of an MMU section */
254enum {
255 MMU_SECTION_SHIFT = 20,
256 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
257};
258
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500259#ifdef CONFIG_ARMV7
260/* TTBR0 bits */
261#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
262#define TTBR0_RGN_NC (0 << 3)
263#define TTBR0_RGN_WBWA (1 << 3)
264#define TTBR0_RGN_WT (2 << 3)
265#define TTBR0_RGN_WB (3 << 3)
266/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
267#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
268#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
269#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
270#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
271#endif
272
Simon Glassa4f20792012-10-17 13:24:53 +0000273/**
Simon Glassa4f20792012-10-17 13:24:53 +0000274 * Register an update to the page tables, and flush the TLB
275 *
276 * \param start start address of update in page table
277 * \param stop stop address of update in page table
278 */
279void mmu_page_table_flush(unsigned long start, unsigned long stop);
280
Thierry Redingc97d9742014-12-09 22:25:22 -0700281#ifdef CONFIG_SYS_NONCACHED_MEMORY
282void noncached_init(void);
283phys_addr_t noncached_alloc(size_t size, size_t align);
284#endif /* CONFIG_SYS_NONCACHED_MEMORY */
285
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200286#endif /* __ASSEMBLY__ */
287
288#define arch_align_stack(x) (x)
289
290#endif /* __KERNEL__ */
291
David Feng85fd5f12013-12-14 11:47:35 +0800292#endif /* CONFIG_ARM64 */
293
Siva Durga Prasad Paladuguba2432a2015-06-26 18:05:07 +0530294#ifndef __ASSEMBLY__
295/**
296 * Change the cache settings for a region.
297 *
298 * \param start start address of memory region to change
299 * \param size size of memory region to change
300 * \param option dcache option to select
301 */
302void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
303 enum dcache_option option);
304
305#endif /* __ASSEMBLY__ */
306
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200307#endif