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git01.mediatek.com / filogic / uboot / d894f7a05a06a25007b0455efe31525f3300c8a6 / . / arch / arm / mach-k3 / r5 / r5_mpu.c
blob: 3dbbcaee5f338eaa1e25486da26f7bb478f48114 [file] [log] [blame]
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * K3: R5 MPU region definitions
4 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530[diff] [blame]6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
Andrew Davis267bb9c2023-11-14 09:59:48 -0600[diff] [blame]9#include <config.h>
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530[diff] [blame]10#include <asm/io.h>
11#include <linux/kernel.h>
Andrew Davis267bb9c2023-11-14 09:59:48 -0600[diff] [blame]12#include <asm/armv7_mpu.h>
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530[diff] [blame]13
14struct mpu_region_config k3_mpu_regions[16] = {
15 /*
16 * Make all 4GB as Device Memory and not executable. We are overriding
17 * it with next region for any requirement.
18 */
19 {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED,
20 REGION_4GB},
21
22 /* SPL code area marking it as WB and Write allocate. */
23 {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW,
24 O_I_WB_RD_WR_ALLOC, REGION_8MB},
25
26 /* U-Boot's code area marking it as WB and Write allocate */
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]27 {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530[diff] [blame]28 O_I_WB_RD_WR_ALLOC, REGION_2GB},
Keerthy305b92c2020-02-12 13:55:05 +0530[diff] [blame]29 /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
30 {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
31 REGION_8MB},
Lokesh Vutlac1e60e82018-11-02 19:51:03 +0530[diff] [blame]32 {0x0, 4, 0x0, 0x0, 0x0, 0x0},
33 {0x0, 5, 0x0, 0x0, 0x0, 0x0},
34 {0x0, 6, 0x0, 0x0, 0x0, 0x0},
35 {0x0, 7, 0x0, 0x0, 0x0, 0x0},
36 {0x0, 8, 0x0, 0x0, 0x0, 0x0},
37 {0x0, 9, 0x0, 0x0, 0x0, 0x0},
38 {0x0, 10, 0x0, 0x0, 0x0, 0x0},
39 {0x0, 11, 0x0, 0x0, 0x0, 0x0},
40 {0x0, 12, 0x0, 0x0, 0x0, 0x0},
41 {0x0, 13, 0x0, 0x0, 0x0, 0x0},
42 {0x0, 14, 0x0, 0x0, 0x0, 0x0},
43 {0x0, 15, 0x0, 0x0, 0x0, 0x0},
44};
45
46void setup_k3_mpu_regions(void)
47{
48 setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
49}