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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yangec02b3c2017-02-23 15:37:51 +08002/*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
Kever Yangec02b3c2017-02-23 15:37:51 +08004 */
5
6#include <common.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +08007#include <asm/arch-rockchip/hardware.h>
Kever Yangec02b3c2017-02-23 15:37:51 +08008#include <asm/armv8/mmu.h>
9#include <asm/io.h>
10
Kever Yangc2053262017-06-23 16:11:11 +080011DECLARE_GLOBAL_DATA_PTR;
12
Kever Yangec02b3c2017-02-23 15:37:51 +080013static struct mm_region rk3328_mem_map[] = {
14 {
15 .virt = 0x0UL,
16 .phys = 0x0UL,
Kever Yang6cd0cab2017-06-13 21:00:12 +080017 .size = 0xff000000UL,
Kever Yangec02b3c2017-02-23 15:37:51 +080018 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
19 PTE_BLOCK_INNER_SHARE
20 }, {
Kever Yang6cd0cab2017-06-13 21:00:12 +080021 .virt = 0xff000000UL,
22 .phys = 0xff000000UL,
23 .size = 0x1000000UL,
Kever Yangec02b3c2017-02-23 15:37:51 +080024 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
25 PTE_BLOCK_NON_SHARE |
26 PTE_BLOCK_PXN | PTE_BLOCK_UXN
27 }, {
28 /* List terminator */
29 0,
30 }
31};
32
33struct mm_region *mem_map = rk3328_mem_map;
34
Kever Yangc2053262017-06-23 16:11:11 +080035int dram_init_banksize(void)
36{
37 size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
38
39 /* Reserve 0x200000 for ATF bl31 */
40 gd->bd->bi_dram[0].start = 0x200000;
41 gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
42
43 return 0;
44}
45
Kever Yangec02b3c2017-02-23 15:37:51 +080046int arch_cpu_init(void)
47{
48 /* We do some SoC one time setting here. */
49
50 return 0;
51}