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git01.mediatek.com / filogic / uboot / d880629fdb20664bf82deef08d49e0d9e9f5db16 / . / arch / arm / dts / dra7-evm-u-boot.dtsi
blob: f1ff5f673319781f53c1c794ba467af6642f30d2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Jean-Jacques Hiblot0296b602017-09-15 12:39:41 +0200[diff] [blame]2/*
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
Jean-Jacques Hiblot0296b602017-09-15 12:39:41 +0200[diff] [blame]4 */
5
6#include "omap5-u-boot.dtsi"
Keerthy5d339ff2022-01-27 13:16:59 +0100[diff] [blame]7#include "dra7-ipu-common-early-boot.dtsi"
Jean-Jacques Hiblot0296b602017-09-15 12:39:41 +0200[diff] [blame]8
9&pcf_gpio_21{
10 u-boot,i2c-offset-len = <0>;
11};
12
13&pcf_hdmi{
14 u-boot,i2c-offset-len = <0>;
15};
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]16
17&mmc2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]19};
20
21&mmc2_pins_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]23};
24
25&mmc2_pins_ddr_rev20 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]27};
28
29&mmc2_pins_hs200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]31};
32
33&mmc2_iodelay_hs200_rev20_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]35};
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]36
37&omap_dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]39};
40
41&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]43 dr_mode = "peripheral";
44};
45
46&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]48};
49
50&usb3_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]52};