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Stefan Roesec6bc1db2012-01-03 16:49:01 +01001/*
2 * (C) Copyright 2000-2009
3 * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
4 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
5 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesec6bc1db2012-01-03 16:49:01 +01007 */
8
9#include <common.h>
10#include <asm/hardware.h>
11#include <asm/io.h>
12#include <asm/arch/spr_misc.h>
13#include <asm/arch/spr_defs.h>
14
Stefan Roesec6bc1db2012-01-03 16:49:01 +010015static void sel_1v8(void)
16{
17 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
18 u32 ddr1v8, ddr2v5;
19
20 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
21 ddr2v5 &= 0x8080ffc0;
22 ddr2v5 |= 0x78000003;
23 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
24
25 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
26 ddr1v8 &= 0x8080ffc0;
27 ddr1v8 |= 0x78000010;
28 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
29
30 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
31 ;
32}
33
34static void sel_2v5(void)
35{
36 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
37 u32 ddr1v8, ddr2v5;
38
39 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
40 ddr1v8 &= 0x8080ffc0;
41 ddr1v8 |= 0x78000003;
42 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
43
44 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
45 ddr2v5 &= 0x8080ffc0;
46 ddr2v5 |= 0x78000010;
47 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
48
49 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
50 ;
51}
52
53/*
54 * plat_ddr_init:
55 */
56void plat_ddr_init(void)
57{
58 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
59 u32 ddrpad;
60 u32 core3v3, ddr1v8, ddr2v5;
61
62 /* DDR pad register configurations */
63 ddrpad = readl(&misc_p->ddr_pad);
64 ddrpad &= ~DDR_PAD_CNF_MSK;
65
66#if (CONFIG_DDR_HCLK)
67 ddrpad |= 0xEAAB;
68#elif (CONFIG_DDR_2HCLK)
69 ddrpad |= 0xEAAD;
70#elif (CONFIG_DDR_PLL2)
71 ddrpad |= 0xEAAD;
72#endif
73 writel(ddrpad, &misc_p->ddr_pad);
74
75 /* Compensation register configurations */
76 core3v3 = readl(&misc_p->core_3v3_compensation);
77 core3v3 &= 0x8080ffe0;
78 core3v3 |= 0x78000002;
79 writel(core3v3, &misc_p->core_3v3_compensation);
80
81 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
82 ddr1v8 &= 0x8080ffc0;
83 ddr1v8 |= 0x78000004;
84 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
85
86 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
87 ddr2v5 &= 0x8080ffc0;
88 ddr2v5 |= 0x78000004;
89 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
90
91 if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
92 /* Software memory configuration */
93 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
94 sel_1v8();
95 else
96 sel_2v5();
97 } else {
98 /* Hardware memory configuration */
99 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
100 sel_1v8();
101 else
102 sel_2v5();
103 }
104}
105
106/*
107 * soc_init:
108 */
109void soc_init(void)
110{
111 /* Nothing to be done for SPEAr600 */
112}
113
114/*
115 * xxx_boot_selected:
116 *
York Sun4a598092013-04-01 11:29:11 -0700117 * return true if the particular booting option is selected
118 * return false otherwise
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100119 */
120static u32 read_bootstrap(void)
121{
122 return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
123 & CONFIG_SPEAR_BOOTSTRAPMASK;
124}
125
126int snor_boot_selected(void)
127{
128 u32 bootstrap = read_bootstrap();
129
130 if (SNOR_BOOT_SUPPORTED) {
131 /* Check whether SNOR boot is selected */
132 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
133 CONFIG_SPEAR_ONLYSNORBOOT)
York Sun4a598092013-04-01 11:29:11 -0700134 return true;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100135
136 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
137 CONFIG_SPEAR_NORNAND8BOOT)
York Sun4a598092013-04-01 11:29:11 -0700138 return true;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100139
140 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
141 CONFIG_SPEAR_NORNAND16BOOT)
York Sun4a598092013-04-01 11:29:11 -0700142 return true;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100143 }
144
York Sun4a598092013-04-01 11:29:11 -0700145 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100146}
147
148int nand_boot_selected(void)
149{
150 u32 bootstrap = read_bootstrap();
151
152 if (NAND_BOOT_SUPPORTED) {
153 /* Check whether NAND boot is selected */
154 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
155 CONFIG_SPEAR_NORNAND8BOOT)
York Sun4a598092013-04-01 11:29:11 -0700156 return true;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100157
158 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
159 CONFIG_SPEAR_NORNAND16BOOT)
York Sun4a598092013-04-01 11:29:11 -0700160 return true;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100161 }
162
York Sun4a598092013-04-01 11:29:11 -0700163 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100164}
165
166int pnor_boot_selected(void)
167{
168 /* Parallel NOR boot is not selected in any SPEAr600 revision */
York Sun4a598092013-04-01 11:29:11 -0700169 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100170}
171
172int usb_boot_selected(void)
173{
174 u32 bootstrap = read_bootstrap();
175
176 if (USB_BOOT_SUPPORTED) {
177 /* Check whether USB boot is selected */
178 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
York Sun4a598092013-04-01 11:29:11 -0700179 return true;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100180 }
181
York Sun4a598092013-04-01 11:29:11 -0700182 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100183}
184
185int tftp_boot_selected(void)
186{
187 /* TFTP boot is not selected in any SPEAr600 revision */
York Sun4a598092013-04-01 11:29:11 -0700188 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100189}
190
191int uart_boot_selected(void)
192{
193 /* UART boot is not selected in any SPEAr600 revision */
York Sun4a598092013-04-01 11:29:11 -0700194 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100195}
196
197int spi_boot_selected(void)
198{
199 /* SPI boot is not selected in any SPEAr600 revision */
York Sun4a598092013-04-01 11:29:11 -0700200 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100201}
202
203int i2c_boot_selected(void)
204{
205 /* I2C boot is not selected in any SPEAr600 revision */
York Sun4a598092013-04-01 11:29:11 -0700206 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100207}
208
209int mmc_boot_selected(void)
210{
York Sun4a598092013-04-01 11:29:11 -0700211 return false;
Stefan Roesec6bc1db2012-01-03 16:49:01 +0100212}
213
214void plat_late_init(void)
215{
216 spear_late_init();
217}