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git01.mediatek.com / filogic / uboot / d84f8cdd6e085087172b613528093e8370ef503c / . / arch / arm / mach-k3 / r5 / j784s4 / clk-data.c
blob: 97d969271ecdf571d493366d1130ba52dc78adc2 [file] [log] [blame]
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * J784S4 specific clock platform data
4 *
5 * This file is auto generated. Please do not hand edit and report any issues
6 * to Bryan Brattlof <bb@ti.com>.
7 *
8 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 */
10
11#include <linux/clk-provider.h>
12#include "k3-clk.h"
13
14static const char * const gluelogic_hfosc0_clkout_parents[] = {
15 "osc_19_2_mhz",
16 "osc_20_mhz",
17 "osc_24_mhz",
18 "osc_25_mhz",
19 "osc_26_mhz",
20 "osc_27_mhz",
21};
22
23static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
24 "board_0_mcu_ospi0_dqs_out",
25 "fss_mcu_0_ospi_0_ospi_oclk_clk",
26};
27
28static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
29 "board_0_mcu_ospi1_dqs_out",
30 "fss_mcu_0_ospi_1_ospi_oclk_clk",
31};
32
33static const char * const wkup_fref_clksel_out0_parents[] = {
34 "gluelogic_hfosc0_clkout",
35 "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
36};
37
38static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
39 "wkup_fref_clksel_out0",
40 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
41};
42
43static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
44 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
45 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
46};
47
48static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
49 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
50 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
51};
52
53static const char * const wkup_gpio0_clksel_out0_parents[] = {
54 "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
55 "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
56 "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
57 "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
58};
59
60static const char * const mcu_usart_clksel_out0_parents[] = {
61 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
62 "postdiv3_16fft_main_1_hsdivout5_clk",
63};
64
65static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
66 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
67 "gluelogic_hfosc0_clkout",
68};
69
Bhavya Kapoord84f8cd2024-10-07 16:37:09 +0530[diff] [blame^]70static const char * const wkup_usart_clksel_out0_parents[] = {
71 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
72 "postdiv3_16fft_main_1_hsdivout5_clk",
73};
74
75static const char * const wkup_usart_mcupll_bypass_out0_parents[] = {
76 "wkup_usart_clksel_out0",
77 "gluelogic_hfosc0_clkout",
78};
79
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]80static const char * const main_pll_hfosc_sel_out0_parents[] = {
81 "gluelogic_hfosc0_clkout",
82 "board_0_hfosc1_clk_out",
83};
84
85static const char * const main_pll_hfosc_sel_out1_parents[] = {
86 "gluelogic_hfosc0_clkout",
87 "board_0_hfosc1_clk_out",
88};
89
90static const char * const main_pll_hfosc_sel_out12_parents[] = {
91 "gluelogic_hfosc0_clkout",
92 "board_0_hfosc1_clk_out",
93};
94
95static const char * const main_pll_hfosc_sel_out19_parents[] = {
96 "gluelogic_hfosc0_clkout",
97 "board_0_hfosc1_clk_out",
98};
99
100static const char * const main_pll_hfosc_sel_out2_parents[] = {
101 "gluelogic_hfosc0_clkout",
102 "board_0_hfosc1_clk_out",
103};
104
105static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
106 "gluelogic_hfosc0_clkout",
107 "board_0_hfosc1_clk_out",
108};
109
110static const char * const main_pll_hfosc_sel_out27_0_parents[] = {
111 "gluelogic_hfosc0_clkout",
112 "board_0_hfosc1_clk_out",
113};
114
115static const char * const main_pll_hfosc_sel_out28_parents[] = {
116 "gluelogic_hfosc0_clkout",
117 "board_0_hfosc1_clk_out",
118};
119
120static const char * const main_pll_hfosc_sel_out3_parents[] = {
121 "gluelogic_hfosc0_clkout",
122 "board_0_hfosc1_clk_out",
123};
124
125static const char * const main_pll_hfosc_sel_out7_parents[] = {
126 "gluelogic_hfosc0_clkout",
127 "board_0_hfosc1_clk_out",
128};
129
130static const char * const main_pll_hfosc_sel_out8_parents[] = {
131 "gluelogic_hfosc0_clkout",
132 "board_0_hfosc1_clk_out",
133};
134
135static const char * const usb0_refclk_sel_out0_parents[] = {
136 "gluelogic_hfosc0_clkout",
137 "board_0_hfosc1_clk_out",
138};
139
140static const char * const emmcsd1_lb_clksel_out0_parents[] = {
141 "board_0_mmc1_clklb_out",
142 "board_0_mmc1_clk_out",
143};
144
145static const char * const mcu_clkout_mux_out0_parents[] = {
146 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
Emanuele Ghidolifb589362024-06-17 11:22:01 +0200[diff] [blame]147 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]148};
149
150static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
151 "main_pll_hfosc_sel_out0",
152 "hsdiv4_16fft_main_0_hsdivout0_clk",
153};
154
155static const char * const dpi0_ext_clksel_out0_parents[] = {
156 "hsdiv1_16fft_main_19_hsdivout0_clk",
157 "board_0_vout0_extpclkin_out",
158};
159
160static const char * const emmcsd_refclk_sel_out0_parents[] = {
161 "hsdiv4_16fft_main_0_hsdivout2_clk",
162 "hsdiv4_16fft_main_1_hsdivout2_clk",
163 "hsdiv4_16fft_main_2_hsdivout2_clk",
164 "hsdiv4_16fft_main_3_hsdivout2_clk",
165};
166
167static const char * const emmcsd_refclk_sel_out1_parents[] = {
168 "hsdiv4_16fft_main_0_hsdivout2_clk",
169 "hsdiv4_16fft_main_1_hsdivout2_clk",
170 "hsdiv4_16fft_main_2_hsdivout2_clk",
171 "hsdiv4_16fft_main_3_hsdivout2_clk",
172};
173
174static const char * const gtc_clk_mux_out0_parents[] = {
175 "hsdiv4_16fft_main_3_hsdivout1_clk",
176 "postdiv3_16fft_main_0_hsdivout6_clk",
177 "board_0_mcu_cpts0_rft_clk_out",
178 "board_0_cpts0_rft_clk_out",
179 "board_0_mcu_ext_refclk0_out",
180 "board_0_ext_refclk1_out",
181 NULL,
182 NULL,
183 NULL,
184 NULL,
185 NULL,
186 NULL,
187 NULL,
188 NULL,
189 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
190 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
191};
192
193static const struct clk_data clk_list[] = {
194 CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
195 CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
196 CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
197 CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
198 CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
199 CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
200 CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
201 CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
202 CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
203 CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
204 CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
205 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
206 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
207 CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
208 CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
209 CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
210 CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
211 CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
212 CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
213 CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
214 CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
215 CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
216 CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
217 CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
218 CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
Bhavya Kapoord84f8cd2024-10-07 16:37:09 +0530[diff] [blame^]219 CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0, 96000000),
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]220 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
221 CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
222 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
223 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
224 CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
225 CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
226 CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
227 CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
228 CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
Bhavya Kapoord84f8cd2024-10-07 16:37:09 +0530[diff] [blame^]229 CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
230 CLK_MUX("wkup_usart_mcupll_bypass_out0", wkup_usart_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]231 CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
232 CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
233 CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
234 CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
235 CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
236 CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
237 CLK_MUX("main_pll_hfosc_sel_out27_0", main_pll_hfosc_sel_out27_0_parents, 2, 0x430080ec, 0, 1, 0),
238 CLK_MUX("main_pll_hfosc_sel_out28", main_pll_hfosc_sel_out28_parents, 2, 0x430080f0, 0, 1, 0),
239 CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
240 CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
241 CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
242 CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
243 CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
244 CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
245 CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
246 CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
247 CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
248 CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
249 CLK_FIXED_RATE("board_0_tck_out", 0, 0),
250 CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
251 CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
252 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
253 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
254 CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000),
255 CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
256 CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
257 CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
258 CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
259 CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
260 CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
261 CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
262 CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
263 CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
264 CLK_PLL("pllfracf2_ssmod_16fft_main_27_foutvcop_clk", "main_pll_hfosc_sel_out27_0", 0x69b000, 0),
265 CLK_PLL("pllfracf2_ssmod_16fft_main_28_foutvcop_clk", "main_pll_hfosc_sel_out28", 0x69c000, 0),
266 CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0, 2000000000),
267 CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
268 CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
269 CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
270 CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
271 CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
272 CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
273 CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
274 CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
275 CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
276 CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
277 CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0),
278 CLK_DIV("hsdiv0_16fft_main_28_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_28_foutvcop_clk", 0x69c080, 0, 7, 0, 0),
279 CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
280 CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
281 CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
282 CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
283 CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
284 CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
285 CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
286 CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
287 CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
288 CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
289 CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
290 CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
291 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
292 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
293 CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
294 CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
295 CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
296 CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
297 CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
298 CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
299 CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
300 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
301 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
302};
303
304static const struct dev_clk soc_dev_clk_data[] = {
305 DEV_CLK(198, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
306 DEV_CLK(198, 3, "hsdiv0_16fft_main_7_hsdivout0_clk"),
307 DEV_CLK(198, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
308 DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
309 DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
310 DEV_CLK(61, 0, "gtc_clk_mux_out0"),
311 DEV_CLK(61, 1, "hsdiv4_16fft_main_3_hsdivout1_clk"),
312 DEV_CLK(61, 2, "postdiv3_16fft_main_0_hsdivout6_clk"),
313 DEV_CLK(61, 3, "board_0_mcu_cpts0_rft_clk_out"),
314 DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"),
315 DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
316 DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
317 DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
318 DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
319 DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
320 DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
321 DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
322 DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
323 DEV_CLK(78, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
324 DEV_CLK(78, 4, "gluelogic_hfosc0_clkout"),
325 DEV_CLK(78, 5, "board_0_hfosc1_clk_out"),
326 DEV_CLK(78, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
327 DEV_CLK(78, 8, "gluelogic_hfosc0_clkout"),
328 DEV_CLK(78, 9, "board_0_hfosc1_clk_out"),
329 DEV_CLK(78, 10, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
330 DEV_CLK(78, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
331 DEV_CLK(78, 12, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
332 DEV_CLK(140, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
333 DEV_CLK(140, 2, "emmcsd_refclk_sel_out0"),
334 DEV_CLK(140, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
335 DEV_CLK(140, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
336 DEV_CLK(140, 5, "hsdiv4_16fft_main_2_hsdivout2_clk"),
337 DEV_CLK(140, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
338 DEV_CLK(141, 0, "emmcsd1_lb_clksel_out0"),
339 DEV_CLK(141, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
340 DEV_CLK(141, 4, "emmcsd_refclk_sel_out1"),
341 DEV_CLK(141, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
342 DEV_CLK(141, 6, "hsdiv4_16fft_main_1_hsdivout2_clk"),
343 DEV_CLK(141, 7, "hsdiv4_16fft_main_2_hsdivout2_clk"),
344 DEV_CLK(141, 8, "hsdiv4_16fft_main_3_hsdivout2_clk"),
345 DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
346 DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
347 DEV_CLK(149, 0, "mcu_usart_clksel_out0"),
348 DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
349 DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
350 DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
351 DEV_CLK(157, 174, "mcu_clkout_mux_out0"),
352 DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
Emanuele Ghidolifb589362024-06-17 11:22:01 +0200[diff] [blame]353 DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]354 DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
355 DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
356 DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
357 DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
358 DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
359 DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
360 DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
361 DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
362 DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
363 DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
364 DEV_CLK(157, 359, "dpi0_ext_clksel_out0"),
365 DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"),
366 DEV_CLK(160, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
367 DEV_CLK(160, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
368 DEV_CLK(160, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
369 DEV_CLK(160, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
370 DEV_CLK(160, 8, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
371 DEV_CLK(161, 0, "board_0_mcu_ospi0_dqs_out"),
372 DEV_CLK(161, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
373 DEV_CLK(161, 2, "mcu_ospi0_iclk_sel_out0"),
374 DEV_CLK(161, 3, "board_0_mcu_ospi0_dqs_out"),
375 DEV_CLK(161, 4, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
376 DEV_CLK(161, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
377 DEV_CLK(161, 7, "mcu_ospi_ref_clk_sel_out0"),
378 DEV_CLK(161, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
379 DEV_CLK(161, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
380 DEV_CLK(162, 0, "board_0_mcu_ospi1_dqs_out"),
381 DEV_CLK(162, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
382 DEV_CLK(162, 2, "mcu_ospi1_iclk_sel_out0"),
383 DEV_CLK(162, 3, "board_0_mcu_ospi1_dqs_out"),
384 DEV_CLK(162, 4, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
385 DEV_CLK(162, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
386 DEV_CLK(162, 7, "mcu_ospi_ref_clk_sel_out1"),
387 DEV_CLK(162, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
388 DEV_CLK(162, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
389 DEV_CLK(167, 0, "wkup_gpio0_clksel_out0"),
390 DEV_CLK(178, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
391 DEV_CLK(178, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
392 DEV_CLK(188, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
393 DEV_CLK(188, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
394 DEV_CLK(191, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
395 DEV_CLK(191, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
396 DEV_CLK(191, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
397 DEV_CLK(191, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
398 DEV_CLK(192, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
399 DEV_CLK(192, 1, "hsdiv0_16fft_main_26_hsdivout0_clk"),
400 DEV_CLK(192, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
401 DEV_CLK(192, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
402 DEV_CLK(193, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
403 DEV_CLK(193, 1, "hsdiv0_16fft_main_27_hsdivout0_clk"),
404 DEV_CLK(193, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
405 DEV_CLK(193, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
406 DEV_CLK(194, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
407 DEV_CLK(194, 1, "hsdiv0_16fft_main_28_hsdivout0_clk"),
408 DEV_CLK(194, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
409 DEV_CLK(194, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
410 DEV_CLK(201, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
411 DEV_CLK(201, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
412 DEV_CLK(243, 0, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
413 DEV_CLK(243, 1, "gluelogic_hfosc0_clkout"),
414 DEV_CLK(243, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
415 DEV_CLK(279, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
416 DEV_CLK(279, 1, "board_0_wkup_i2c0_scl_out"),
417 DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"),
418 DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
419 DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"),
420 DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"),
421 DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
422 DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"),
423 DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
Bhavya Kapoord84f8cd2024-10-07 16:37:09 +0530[diff] [blame^]424 DEV_CLK(397, 0, "wkup_usart_mcupll_bypass_out0"),
425 DEV_CLK(397, 1, "wkup_usart_clksel_out0"),
426 DEV_CLK(397, 2, "gluelogic_hfosc0_clkout"),
427 DEV_CLK(397, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
Apurva Nandanb93ab922024-02-24 01:51:44 +0530[diff] [blame]428 DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
429 DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
430 DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"),
431 DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
432 DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
433 DEV_CLK(398, 21, "usb0_refclk_sel_out0"),
434 DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"),
435 DEV_CLK(398, 23, "board_0_hfosc1_clk_out"),
436 DEV_CLK(398, 28, "board_0_tck_out"),
437};
438
439const struct ti_k3_clk_platdata j784s4_clk_platdata = {
440 .clk_list = clk_list,
441 .clk_list_cnt = ARRAY_SIZE(clk_list),
442 .soc_dev_clk_data = soc_dev_clk_data,
443 .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
444};