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git01.mediatek.com / filogic / uboot / d84ec3a9a5914330b5d4491cc756bfd3e8541f55 / . / arch / powerpc / cpu / mpc5xxx / u-boot.lds
blob: 1f46eadb5d09f7b3055b631846f09e8fb5266f28 [file] [log] [blame]
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]1/*
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]2 * (C) Copyright 2003-2010
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(powerpc)
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]25
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]26SECTIONS
27{
28 /* Read-only sections, merged into text segment: */
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]29 .text :
30 {
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]31 arch/powerpc/cpu/mpc5xxx/start.o (.text*)
32 arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
33 *(.text*)
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]34 . = ALIGN(16);
Trent Piepho4438e5e2009-02-18 15:22:05 -0800[diff] [blame]35 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]36 }
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]37
38 /* Read-write section, merged into data segment: */
39 . = (. + 0x0FFF) & 0xFFFFF000;
40 _erotext = .;
41 PROVIDE (erotext = .);
42 .reloc :
43 {
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]44 _GOT2_TABLE_ = .;
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]45 KEEP(*(.got2))
Joakim Tjernlund42126a62010-12-03 17:30:37 +0100[diff] [blame]46 KEEP(*(.got))
47 PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]48 _FIXUP_TABLE_ = .;
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]49 KEEP(*(.fixup))
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]50 }
Joakim Tjernlund42126a62010-12-03 17:30:37 +0100[diff] [blame]51 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]52 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
53
54 .data :
55 {
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]56 *(.data*)
57 *(.sdata*)
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]58 }
59 _edata = .;
60 PROVIDE (edata = .);
61
62 . = .;
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]63
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]64 . = ALIGN(4);
65 .u_boot_list : {
66 #include <u-boot.lst>
67 }
68
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]69
70 . = .;
71 __start___ex_table = .;
72 __ex_table : { *(__ex_table) }
73 __stop___ex_table = .;
74
75 . = ALIGN(4096);
76 __init_begin = .;
77 .text.init : { *(.text.init) }
78 .data.init : { *(.data.init) }
79 . = ALIGN(4096);
80 __init_end = .;
81
82 __bss_start = .;
Wolfgang Denk828a9782008-01-12 20:31:39 +0100[diff] [blame]83 .bss (NOLOAD) :
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]84 {
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]85 *(COMMON)
Wolfgang Denk01fd9152010-11-23 13:20:22 +0100[diff] [blame]86 *(.bss*)
87 *(.sbss*)
Selvamuthukumard2454ba2008-10-16 22:54:03 +0530[diff] [blame]88 . = ALIGN(4);
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]89 }
Po-Yu Chuangcedbf4b2011-03-01 22:59:59 +0000[diff] [blame]90 __bss_end__ = . ;
Grant Likely17208ae2007-07-03 00:32:58 -0600[diff] [blame]91 PROVIDE (end = .);
92}