Scott Wood | 2fa1391 | 2007-04-16 14:34:21 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Freescale Semiconductor, Inc. 2007 |
| 3 | * |
| 4 | * Author: Scott Wood <scottwood@freescale.com>, |
| 5 | * with some bits from older board-specific PCI initialization. |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #include <common.h> |
| 27 | #include <pci.h> |
Kim Phillips | 3c6f3b7 | 2007-07-25 19:25:28 -0500 | [diff] [blame] | 28 | |
| 29 | #if defined(CONFIG_OF_LIBFDT) |
| 30 | #include <libfdt.h> |
Kim Phillips | 3c6f3b7 | 2007-07-25 19:25:28 -0500 | [diff] [blame] | 31 | #elif defined(CONFIG_OF_FLAT_TREE) |
Kim Phillips | ffc21c0 | 2007-04-25 12:34:38 -0500 | [diff] [blame] | 32 | #include <ft_build.h> |
Kim Phillips | 3c6f3b7 | 2007-07-25 19:25:28 -0500 | [diff] [blame] | 33 | #endif |
| 34 | |
Scott Wood | 2fa1391 | 2007-04-16 14:34:21 -0500 | [diff] [blame] | 35 | #include <asm/mpc8349_pci.h> |
| 36 | |
| 37 | #ifdef CONFIG_83XX_GENERIC_PCI |
| 38 | #define MAX_BUSES 2 |
| 39 | |
| 40 | DECLARE_GLOBAL_DATA_PTR; |
| 41 | |
| 42 | static struct pci_controller pci_hose[MAX_BUSES]; |
| 43 | static int pci_num_buses; |
| 44 | |
| 45 | static void pci_init_bus(int bus, struct pci_region *reg) |
| 46 | { |
| 47 | volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
| 48 | volatile pot83xx_t *pot = immr->ios.pot; |
| 49 | volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus]; |
| 50 | struct pci_controller *hose = &pci_hose[bus]; |
| 51 | u32 dev; |
| 52 | u16 reg16; |
| 53 | int i; |
| 54 | |
| 55 | if (bus == 1) |
| 56 | pot += 3; |
| 57 | |
| 58 | /* Setup outbound translation windows */ |
| 59 | for (i = 0; i < 3; i++, reg++, pot++) { |
| 60 | if (reg->size == 0) |
| 61 | break; |
| 62 | |
| 63 | hose->regions[i] = *reg; |
| 64 | hose->region_count++; |
| 65 | |
| 66 | pot->potar = reg->bus_start >> 12; |
| 67 | pot->pobar = reg->phys_start >> 12; |
| 68 | pot->pocmr = ~(reg->size - 1) >> 12; |
| 69 | |
| 70 | if (reg->flags & PCI_REGION_IO) |
| 71 | pot->pocmr |= POCMR_IO; |
| 72 | #ifdef CONFIG_83XX_PCI_STREAMING |
| 73 | else if (reg->flags & PCI_REGION_PREFETCH) |
| 74 | pot->pocmr |= POCMR_SE; |
| 75 | #endif |
| 76 | |
| 77 | if (bus == 1) |
| 78 | pot->pocmr |= POCMR_DST; |
| 79 | |
| 80 | pot->pocmr |= POCMR_EN; |
| 81 | } |
| 82 | |
| 83 | /* Point inbound translation at RAM */ |
| 84 | pci_ctrl->pitar1 = 0; |
| 85 | pci_ctrl->pibar1 = 0; |
| 86 | pci_ctrl->piebar1 = 0; |
| 87 | pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | |
| 88 | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); |
| 89 | |
| 90 | i = hose->region_count++; |
| 91 | hose->regions[i].bus_start = 0; |
| 92 | hose->regions[i].phys_start = 0; |
| 93 | hose->regions[i].size = gd->ram_size; |
| 94 | hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; |
| 95 | |
| 96 | hose->first_busno = 0; |
| 97 | hose->last_busno = 0xff; |
| 98 | |
| 99 | pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80, |
| 100 | CFG_IMMR + 0x8304 + bus * 0x80); |
| 101 | |
| 102 | pci_register_hose(hose); |
| 103 | |
| 104 | /* |
| 105 | * Write to Command register |
| 106 | */ |
| 107 | reg16 = 0xff; |
| 108 | dev = PCI_BDF(hose->first_busno, 0, 0); |
| 109 | pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); |
| 110 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 111 | pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
| 112 | |
| 113 | /* |
| 114 | * Clear non-reserved bits in status register. |
| 115 | */ |
| 116 | pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
| 117 | pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
| 118 | pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
| 119 | |
| 120 | #ifdef CONFIG_PCI_SCAN_SHOW |
| 121 | printf("PCI: Bus Dev VenId DevId Class Int\n"); |
| 122 | #endif |
| 123 | /* |
| 124 | * Hose scan. |
| 125 | */ |
| 126 | hose->last_busno = pci_hose_scan(hose); |
| 127 | } |
| 128 | |
| 129 | /* |
| 130 | * The caller must have already set OCCR, and the PCI_LAW BARs |
| 131 | * must have been set to cover all of the requested regions. |
| 132 | * |
| 133 | * If fewer than three regions are requested, then the region |
| 134 | * list is terminated with a region of size 0. |
| 135 | */ |
| 136 | void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) |
| 137 | { |
| 138 | volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
| 139 | int i; |
| 140 | |
| 141 | if (num_buses > MAX_BUSES) { |
| 142 | printf("%d PCI buses requsted, %d supported\n", |
| 143 | num_buses, MAX_BUSES); |
| 144 | |
| 145 | num_buses = MAX_BUSES; |
| 146 | } |
| 147 | |
| 148 | pci_num_buses = num_buses; |
| 149 | |
| 150 | /* |
| 151 | * Release PCI RST Output signal. |
| 152 | * Power on to RST high must be at least 100 ms as per PCI spec. |
| 153 | * On warm boots only 1 ms is required. |
| 154 | */ |
| 155 | udelay(warmboot ? 1000 : 100000); |
| 156 | |
| 157 | for (i = 0; i < num_buses; i++) |
| 158 | immr->pci_ctrl[i].gcr = 1; |
| 159 | |
| 160 | /* |
| 161 | * RST high to first config access must be at least 2^25 cycles |
| 162 | * as per PCI spec. This could be cut in half if we know we're |
| 163 | * running at 66MHz. This could be insufficiently long if we're |
| 164 | * running the PCI bus at significantly less than 33MHz. |
| 165 | */ |
| 166 | udelay(1020000); |
| 167 | |
| 168 | for (i = 0; i < num_buses; i++) |
| 169 | pci_init_bus(i, reg[i]); |
| 170 | } |
| 171 | |
Kim Phillips | 3c6f3b7 | 2007-07-25 19:25:28 -0500 | [diff] [blame] | 172 | #if defined(CONFIG_OF_LIBFDT) |
| 173 | void ft_pci_setup(void *blob, bd_t *bd) |
| 174 | { |
| 175 | int nodeoffset; |
| 176 | int err; |
| 177 | int tmp[2]; |
| 178 | |
| 179 | if (pci_num_buses < 1) |
| 180 | return; |
| 181 | |
| 182 | nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); |
| 183 | if (nodeoffset >= 0) { |
| 184 | tmp[0] = cpu_to_be32(pci_hose[0].first_busno); |
| 185 | tmp[1] = cpu_to_be32(pci_hose[0].last_busno); |
Kim Phillips | 2141681 | 2007-08-15 22:30:33 -0500 | [diff] [blame] | 186 | err = fdt_setprop(blob, nodeoffset, "bus-range", |
| 187 | tmp, sizeof(tmp)); |
| 188 | |
| 189 | tmp[0] = cpu_to_be32(gd->pci_clk); |
| 190 | err = fdt_setprop(blob, nodeoffset, "clock-frequency", |
| 191 | tmp, sizeof(tmp[0])); |
Kim Phillips | 3c6f3b7 | 2007-07-25 19:25:28 -0500 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | if (pci_num_buses < 2) |
| 195 | return; |
| 196 | |
| 197 | nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); |
| 198 | if (nodeoffset >= 0) { |
| 199 | tmp[0] = cpu_to_be32(pci_hose[0].first_busno); |
| 200 | tmp[1] = cpu_to_be32(pci_hose[0].last_busno); |
Kim Phillips | 2141681 | 2007-08-15 22:30:33 -0500 | [diff] [blame] | 201 | err = fdt_setprop(blob, nodeoffset, "bus-range", |
| 202 | tmp, sizeof(tmp)); |
| 203 | |
| 204 | tmp[0] = cpu_to_be32(gd->pci_clk); |
| 205 | err = fdt_setprop(blob, nodeoffset, "clock-frequency", |
| 206 | tmp, sizeof(tmp[0])); |
Kim Phillips | 3c6f3b7 | 2007-07-25 19:25:28 -0500 | [diff] [blame] | 207 | } |
| 208 | } |
| 209 | #elif CONFIG_OF_FLAT_TREE |
Scott Wood | 2fa1391 | 2007-04-16 14:34:21 -0500 | [diff] [blame] | 210 | void ft_pci_setup(void *blob, bd_t *bd) |
| 211 | { |
| 212 | u32 *p; |
| 213 | int len; |
| 214 | |
| 215 | if (pci_num_buses < 1) |
| 216 | return; |
| 217 | |
| 218 | p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
| 219 | if (p) { |
| 220 | p[0] = pci_hose[0].first_busno; |
| 221 | p[1] = pci_hose[0].last_busno; |
| 222 | } |
| 223 | |
| 224 | if (pci_num_buses < 2) |
| 225 | return; |
| 226 | |
| 227 | p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); |
| 228 | if (p) { |
| 229 | p[0] = pci_hose[1].first_busno; |
| 230 | p[1] = pci_hose[1].last_busno; |
| 231 | } |
| 232 | } |
| 233 | #endif /* CONFIG_OF_FLAT_TREE */ |
| 234 | |
| 235 | #endif /* CONFIG_83XX_GENERIC_PCI */ |