blob: aac7b5dc3877bac6450b3ef6dd40aac3143f9bf0 [file] [log] [blame]
Masami Hiramatsu7c741272021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
Masami Hiramatsu7c741272021-06-04 18:45:10 +09009#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
10
11/*
12 * SDRAM (for initialize)
13 */
14#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
15#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
16
17#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
18#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
19
20#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
21
22/*
23 * Boot info
24 */
25#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
Masami Hiramatsu7c741272021-06-04 18:45:10 +090026
27/*
28 * Hardware drivers support
29 */
30
31/* RTC */
32#define CONFIG_SYS_I2C_RTC_ADDR 0x51
33
34/* Serial (pl011) */
35#define UART_CLK (62500000)
36#define CONFIG_SERIAL_MULTI
37#define CONFIG_PL011_SERIAL
38#define CONFIG_PL011_CLOCK UART_CLK
39#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
40
41#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
42
43/* Support MTD */
44#define CONFIG_SYS_MAX_FLASH_BANKS 1
45#define CONFIG_SYS_FLASH_BASE (0x08000000)
46#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
47
48#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
49#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
50
Masami Hiramatsu7c741272021-06-04 18:45:10 +090051#define CONFIG_SYS_CBSIZE 1024
52#define CONFIG_SYS_MAXARGS 128
53#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
54
55/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
56/* #define CONFIG_SYS_PCI_64BIT 1 */
57
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +090058#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
Masami Hiramatsufe1e5582021-07-12 19:36:12 +090059 "mtd mx66u51235f=u-boot.bin raw 200000 100000;" \
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +090060 "fip.bin raw 180000 78000;" \
61 "optee.bin raw 500000 100000\0"
62
Masami Hiramatsu7c741272021-06-04 18:45:10 +090063/* Distro boot settings */
64#ifndef CONFIG_SPL_BUILD
65#ifdef CONFIG_CMD_USB
66#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
67#else
68#define BOOT_TARGET_DEVICE_USB(func)
69#endif
70
71#ifdef CONFIG_CMD_MMC
72#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
73#else
74#define BOOT_TARGET_DEVICE_MMC(func)
75#endif
76
77#ifdef CONFIG_CMD_NVME
78#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
79#else
80#define BOOT_TARGET_DEVICE_NVME(func)
81#endif
82
83#ifdef CONFIG_CMD_SCSI
84#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
85#else
86#define BOOT_TARGET_DEVICE_SCSI(func)
87#endif
88
89#define BOOT_TARGET_DEVICES(func) \
90 BOOT_TARGET_DEVICE_USB(func) \
91 BOOT_TARGET_DEVICE_MMC(func) \
92 BOOT_TARGET_DEVICE_SCSI(func) \
93 BOOT_TARGET_DEVICE_NVME(func) \
94
95#include <config_distro_bootcmd.h>
96#else /* CONFIG_SPL_BUILD */
97#define BOOTENV
98#endif
99
100#define CONFIG_EXTRA_ENV_SETTINGS \
101 "fdt_addr_r=0x9fe00000\0" \
102 "kernel_addr_r=0x90000000\0" \
103 "ramdisk_addr_r=0xa0000000\0" \
104 "scriptaddr=0x88000000\0" \
105 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu1d5afdf2021-06-04 18:45:31 +0900106 DEFAULT_DFU_ALT_INFO \
Masami Hiramatsu7c741272021-06-04 18:45:10 +0900107 BOOTENV
108
109#endif /* __CONFIG_H */