Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Texas Instruments' K3 DDRSS driver |
| 4 | * |
| 5 | * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 9 | #include <config.h> |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 10 | #include <clk.h> |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 11 | #include <div64.h> |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 12 | #include <dm.h> |
| 13 | #include <dm/device_compat.h> |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 14 | #include <fdt_support.h> |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 15 | #include <ram.h> |
| 16 | #include <hang.h> |
| 17 | #include <log.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <power-domain.h> |
| 20 | #include <wait_bit.h> |
Lokesh Vutla | dd01c63 | 2021-05-11 10:22:13 -0500 | [diff] [blame] | 21 | #include <power/regulator.h> |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 22 | |
| 23 | #include "lpddr4_obj_if.h" |
| 24 | #include "lpddr4_if.h" |
| 25 | #include "lpddr4_structs_if.h" |
| 26 | #include "lpddr4_ctl_regs.h" |
| 27 | |
| 28 | #define SRAM_MAX 512 |
| 29 | |
| 30 | #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80 |
| 31 | #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0 |
| 32 | |
Dominic Rath | 6feaf59 | 2022-04-06 11:56:47 +0200 | [diff] [blame] | 33 | #define DDRSS_V2A_CTL_REG 0x0020 |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 34 | #define DDRSS_ECC_CTRL_REG 0x0120 |
Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame] | 35 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 36 | #define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0) |
| 37 | #define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1) |
| 38 | #define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2) |
| 39 | #define DDRSS_ECC_CTRL_REG_WR_ALLOC BIT(4) |
| 40 | |
| 41 | #define DDRSS_ECC_R0_STR_ADDR_REG 0x0130 |
| 42 | #define DDRSS_ECC_R0_END_ADDR_REG 0x0134 |
| 43 | #define DDRSS_ECC_R1_STR_ADDR_REG 0x0138 |
| 44 | #define DDRSS_ECC_R1_END_ADDR_REG 0x013c |
| 45 | #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140 |
| 46 | #define DDRSS_ECC_R2_END_ADDR_REG 0x0144 |
| 47 | #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 |
| 48 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 49 | #define SINGLE_DDR_SUBSYSTEM 0x1 |
| 50 | #define MULTI_DDR_SUBSYSTEM 0x2 |
| 51 | |
Aswath Govindraju | 6324bc7 | 2022-01-25 20:56:30 +0530 | [diff] [blame] | 52 | #define MULTI_DDR_CFG0 0x00114100 |
| 53 | #define MULTI_DDR_CFG1 0x00114104 |
| 54 | #define DDR_CFG_LOAD 0x00114110 |
| 55 | |
| 56 | enum intrlv_gran { |
| 57 | GRAN_128B, |
| 58 | GRAN_512B, |
| 59 | GRAN_2KB, |
| 60 | GRAN_4KB, |
| 61 | GRAN_16KB, |
| 62 | GRAN_32KB, |
| 63 | GRAN_512KB, |
| 64 | GRAN_1GB, |
| 65 | GRAN_1_5GB, |
| 66 | GRAN_2GB, |
| 67 | GRAN_3GB, |
| 68 | GRAN_4GB, |
| 69 | GRAN_6GB, |
| 70 | GRAN_8GB, |
| 71 | GRAN_16GB |
| 72 | }; |
| 73 | |
| 74 | enum intrlv_size { |
| 75 | SIZE_0, |
| 76 | SIZE_128MB, |
| 77 | SIZE_256MB, |
| 78 | SIZE_512MB, |
| 79 | SIZE_1GB, |
| 80 | SIZE_2GB, |
| 81 | SIZE_3GB, |
| 82 | SIZE_4GB, |
| 83 | SIZE_6GB, |
| 84 | SIZE_8GB, |
| 85 | SIZE_12GB, |
| 86 | SIZE_16GB, |
| 87 | SIZE_32GB |
| 88 | }; |
| 89 | |
| 90 | struct k3_ddrss_data { |
| 91 | u32 flags; |
| 92 | }; |
| 93 | |
| 94 | enum ecc_enable { |
| 95 | DISABLE_ALL = 0, |
| 96 | ENABLE_0, |
| 97 | ENABLE_1, |
| 98 | ENABLE_ALL |
| 99 | }; |
| 100 | |
| 101 | enum emif_config { |
| 102 | INTERLEAVE_ALL = 0, |
| 103 | SEPR0, |
| 104 | SEPR1 |
| 105 | }; |
| 106 | |
| 107 | enum emif_active { |
| 108 | EMIF_0 = 1, |
| 109 | EMIF_1, |
| 110 | EMIF_ALL |
| 111 | }; |
| 112 | |
| 113 | struct k3_msmc { |
| 114 | enum intrlv_gran gran; |
| 115 | enum intrlv_size size; |
| 116 | enum ecc_enable enable; |
| 117 | enum emif_config config; |
| 118 | enum emif_active active; |
| 119 | }; |
| 120 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 121 | #define K3_DDRSS_MAX_ECC_REGIONS 3 |
| 122 | |
| 123 | struct k3_ddrss_ecc_region { |
| 124 | u32 start; |
| 125 | u32 range; |
| 126 | }; |
| 127 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 128 | struct k3_ddrss_desc { |
| 129 | struct udevice *dev; |
| 130 | void __iomem *ddrss_ss_cfg; |
| 131 | void __iomem *ddrss_ctrl_mmr; |
Dave Gerlach | fd199dd | 2022-03-17 12:03:42 -0500 | [diff] [blame] | 132 | void __iomem *ddrss_ctl_cfg; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 133 | struct power_domain ddrcfg_pwrdmn; |
| 134 | struct power_domain ddrdata_pwrdmn; |
| 135 | struct clk ddr_clk; |
| 136 | struct clk osc_clk; |
Dave Gerlach | ff4e82b | 2022-04-08 16:46:50 -0500 | [diff] [blame] | 137 | u32 ddr_freq0; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 138 | u32 ddr_freq1; |
| 139 | u32 ddr_freq2; |
| 140 | u32 ddr_fhs_cnt; |
Bryan Brattlof | 2905a46 | 2023-07-17 17:15:26 -0500 | [diff] [blame] | 141 | u32 dram_class; |
Lokesh Vutla | dd01c63 | 2021-05-11 10:22:13 -0500 | [diff] [blame] | 142 | struct udevice *vtt_supply; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 143 | u32 instance; |
| 144 | lpddr4_obj *driverdt; |
| 145 | lpddr4_config config; |
| 146 | lpddr4_privatedata pd; |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 147 | struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; |
| 148 | u64 ecc_reserved_space; |
| 149 | bool ti_ecc_enabled; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 150 | }; |
| 151 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 152 | struct reginitdata { |
| 153 | u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT]; |
| 154 | u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT]; |
| 155 | u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT]; |
| 156 | u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT]; |
| 157 | u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT]; |
| 158 | u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT]; |
| 159 | }; |
| 160 | |
| 161 | #define TH_MACRO_EXP(fld, str) (fld##str) |
| 162 | |
| 163 | #define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK) |
| 164 | #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT) |
| 165 | #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH) |
| 166 | #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR) |
| 167 | #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET) |
| 168 | |
| 169 | #define str(s) #s |
| 170 | #define xstr(s) str(s) |
| 171 | |
| 172 | #define CTL_SHIFT 11 |
| 173 | #define PHY_SHIFT 11 |
| 174 | #define PI_SHIFT 10 |
| 175 | |
| 176 | #define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA |
| 177 | #define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB |
| 178 | |
| 179 | #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\ |
| 180 | char *i, *pstr = xstr(REG); offset = 0;\ |
| 181 | for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\ |
| 182 | offset = offset * 10 + (*i - '0'); } \ |
| 183 | } while (0) |
| 184 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 185 | static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 186 | { |
| 187 | u32 status = 0U; |
| 188 | u32 offset = 0U; |
| 189 | u32 regval = 0U; |
| 190 | u32 dram_class = 0U; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 191 | struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 192 | |
| 193 | TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset); |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 194 | status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 195 | if (status > 0U) { |
| 196 | printf("%s: Failed to read DRAM_CLASS\n", __func__); |
| 197 | hang(); |
| 198 | } |
| 199 | |
| 200 | dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >> |
| 201 | TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD)); |
| 202 | return dram_class; |
| 203 | } |
| 204 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 205 | static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 206 | { |
| 207 | unsigned int req_type, counter; |
| 208 | |
| 209 | for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) { |
| 210 | if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 211 | CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80, |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 212 | true, 10000, false)) { |
| 213 | printf("Timeout during frequency handshake\n"); |
| 214 | hang(); |
| 215 | } |
| 216 | |
| 217 | req_type = readl(ddrss->ddrss_ctrl_mmr + |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 218 | CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 219 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 220 | debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n", |
| 221 | __func__, req_type, counter, ddrss->instance); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 222 | |
| 223 | if (req_type == 1) |
| 224 | clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); |
| 225 | else if (req_type == 2) |
| 226 | clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); |
| 227 | else if (req_type == 0) |
Dave Gerlach | ff4e82b | 2022-04-08 16:46:50 -0500 | [diff] [blame] | 228 | clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 229 | else |
| 230 | printf("%s: Invalid freq request type\n", __func__); |
| 231 | |
| 232 | writel(0x1, ddrss->ddrss_ctrl_mmr + |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 233 | CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 234 | if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 235 | CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80, |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 236 | false, 10, false)) { |
| 237 | printf("Timeout during frequency handshake\n"); |
| 238 | hang(); |
| 239 | } |
| 240 | writel(0x0, ddrss->ddrss_ctrl_mmr + |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 241 | CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 242 | } |
| 243 | } |
| 244 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 245 | static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 246 | { |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 247 | struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 248 | |
| 249 | debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); |
| 250 | |
Bryan Brattlof | 2905a46 | 2023-07-17 17:15:26 -0500 | [diff] [blame] | 251 | switch (ddrss->dram_class) { |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 252 | case DENALI_CTL_0_DRAM_CLASS_DDR4: |
| 253 | break; |
| 254 | case DENALI_CTL_0_DRAM_CLASS_LPDDR4: |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 255 | k3_lpddr4_freq_update(ddrss); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 256 | break; |
| 257 | default: |
| 258 | printf("Unrecognized dram_class cannot update frequency!\n"); |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) |
| 263 | { |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 264 | int ret; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 265 | lpddr4_privatedata *pd = &ddrss->pd; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 266 | |
Bryan Brattlof | 2905a46 | 2023-07-17 17:15:26 -0500 | [diff] [blame] | 267 | ddrss->dram_class = k3_lpddr4_read_ddr_type(pd); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 268 | |
Bryan Brattlof | 2905a46 | 2023-07-17 17:15:26 -0500 | [diff] [blame] | 269 | switch (ddrss->dram_class) { |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 270 | case DENALI_CTL_0_DRAM_CLASS_DDR4: |
| 271 | /* Set to ddr_freq1 from DT for DDR4 */ |
| 272 | ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); |
| 273 | break; |
| 274 | case DENALI_CTL_0_DRAM_CLASS_LPDDR4: |
Dave Gerlach | ff4e82b | 2022-04-08 16:46:50 -0500 | [diff] [blame] | 275 | ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 276 | break; |
| 277 | default: |
| 278 | ret = -EINVAL; |
| 279 | printf("Unrecognized dram_class cannot init frequency!\n"); |
| 280 | } |
| 281 | |
| 282 | if (ret < 0) |
| 283 | dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret); |
| 284 | else |
| 285 | ret = 0; |
| 286 | |
| 287 | return ret; |
| 288 | } |
| 289 | |
| 290 | static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd, |
| 291 | lpddr4_infotype infotype) |
| 292 | { |
| 293 | if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 294 | k3_lpddr4_ack_freq_upd_req(pd); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss) |
| 298 | { |
| 299 | int ret; |
| 300 | |
| 301 | debug("%s(ddrss=%p)\n", __func__, ddrss); |
| 302 | |
| 303 | ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); |
| 304 | if (ret) { |
| 305 | dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); |
| 306 | return ret; |
| 307 | } |
| 308 | |
| 309 | ret = power_domain_on(&ddrss->ddrdata_pwrdmn); |
| 310 | if (ret) { |
| 311 | dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); |
| 312 | return ret; |
| 313 | } |
| 314 | |
Lokesh Vutla | dd01c63 | 2021-05-11 10:22:13 -0500 | [diff] [blame] | 315 | ret = device_get_supply_regulator(ddrss->dev, "vtt-supply", |
| 316 | &ddrss->vtt_supply); |
| 317 | if (ret) { |
| 318 | dev_dbg(ddrss->dev, "vtt-supply not found.\n"); |
| 319 | } else { |
| 320 | ret = regulator_set_value(ddrss->vtt_supply, 3300000); |
| 321 | if (ret) |
| 322 | return ret; |
| 323 | dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n", |
| 324 | regulator_get_value(ddrss->vtt_supply)); |
| 325 | } |
| 326 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | static int k3_ddrss_ofdata_to_priv(struct udevice *dev) |
| 331 | { |
| 332 | struct k3_ddrss_desc *ddrss = dev_get_priv(dev); |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 333 | struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 334 | phys_addr_t reg; |
| 335 | int ret; |
| 336 | |
| 337 | debug("%s(dev=%p)\n", __func__, dev); |
| 338 | |
| 339 | reg = dev_read_addr_name(dev, "cfg"); |
| 340 | if (reg == FDT_ADDR_T_NONE) { |
| 341 | dev_err(dev, "No reg property for DDRSS wrapper logic\n"); |
| 342 | return -EINVAL; |
| 343 | } |
Dave Gerlach | fd199dd | 2022-03-17 12:03:42 -0500 | [diff] [blame] | 344 | ddrss->ddrss_ctl_cfg = (void *)reg; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 345 | |
| 346 | reg = dev_read_addr_name(dev, "ctrl_mmr_lp4"); |
| 347 | if (reg == FDT_ADDR_T_NONE) { |
| 348 | dev_err(dev, "No reg property for CTRL MMR\n"); |
| 349 | return -EINVAL; |
| 350 | } |
| 351 | ddrss->ddrss_ctrl_mmr = (void *)reg; |
| 352 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 353 | reg = dev_read_addr_name(dev, "ss_cfg"); |
| 354 | if (reg == FDT_ADDR_T_NONE) { |
| 355 | dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n"); |
| 356 | ddrss->ddrss_ss_cfg = NULL; |
| 357 | } else { |
| 358 | ddrss->ddrss_ss_cfg = (void *)reg; |
| 359 | } |
| 360 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 361 | ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); |
| 362 | if (ret) { |
| 363 | dev_err(dev, "power_domain_get() failed: %d\n", ret); |
| 364 | return ret; |
| 365 | } |
| 366 | |
| 367 | ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); |
| 368 | if (ret) { |
| 369 | dev_err(dev, "power_domain_get() failed: %d\n", ret); |
| 370 | return ret; |
| 371 | } |
| 372 | |
| 373 | ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk); |
| 374 | if (ret) |
| 375 | dev_err(dev, "clk get failed%d\n", ret); |
| 376 | |
| 377 | ret = clk_get_by_index(dev, 1, &ddrss->osc_clk); |
| 378 | if (ret) |
| 379 | dev_err(dev, "clk get failed for osc clk %d\n", ret); |
| 380 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 381 | /* Reading instance number for multi ddr subystems */ |
| 382 | if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) { |
| 383 | ret = dev_read_u32(dev, "instance", &ddrss->instance); |
| 384 | if (ret) { |
| 385 | dev_err(dev, "missing instance property"); |
| 386 | return -EINVAL; |
| 387 | } |
| 388 | } else { |
| 389 | ddrss->instance = 0; |
| 390 | } |
| 391 | |
Dave Gerlach | ff4e82b | 2022-04-08 16:46:50 -0500 | [diff] [blame] | 392 | ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0); |
| 393 | if (ret) { |
| 394 | ddrss->ddr_freq0 = clk_get_rate(&ddrss->osc_clk); |
| 395 | dev_dbg(dev, |
| 396 | "ddr freq0 not populated, using bypass frequency.\n"); |
| 397 | } |
| 398 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 399 | ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); |
| 400 | if (ret) |
| 401 | dev_err(dev, "ddr freq1 not populated %d\n", ret); |
| 402 | |
| 403 | ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2); |
| 404 | if (ret) |
| 405 | dev_err(dev, "ddr freq2 not populated %d\n", ret); |
| 406 | |
| 407 | ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt); |
| 408 | if (ret) |
| 409 | dev_err(dev, "ddr fhs cnt not populated %d\n", ret); |
| 410 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 411 | ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable"); |
| 412 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 413 | return ret; |
| 414 | } |
| 415 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 416 | void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 417 | { |
| 418 | u32 status = 0U; |
| 419 | u16 configsize = 0U; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 420 | lpddr4_config *config = &ddrss->config; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 421 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 422 | status = ddrss->driverdt->probe(config, &configsize); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 423 | |
| 424 | if ((status != 0) || (configsize != sizeof(lpddr4_privatedata)) |
| 425 | || (configsize > SRAM_MAX)) { |
| 426 | printf("%s: FAIL\n", __func__); |
| 427 | hang(); |
| 428 | } else { |
| 429 | debug("%s: PASS\n", __func__); |
| 430 | } |
| 431 | } |
| 432 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 433 | void k3_lpddr4_init(struct k3_ddrss_desc *ddrss) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 434 | { |
| 435 | u32 status = 0U; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 436 | lpddr4_config *config = &ddrss->config; |
| 437 | lpddr4_obj *driverdt = ddrss->driverdt; |
| 438 | lpddr4_privatedata *pd = &ddrss->pd; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 439 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 440 | if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) { |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 441 | printf("%s: FAIL\n", __func__); |
| 442 | hang(); |
| 443 | } |
| 444 | |
Dave Gerlach | fd199dd | 2022-03-17 12:03:42 -0500 | [diff] [blame] | 445 | config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctl_cfg; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 446 | config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 447 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 448 | status = driverdt->init(pd, config); |
| 449 | |
| 450 | /* linking ddr instance to lpddr4 */ |
| 451 | pd->ddr_instance = (void *)ddrss; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 452 | |
| 453 | if ((status > 0U) || |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 454 | (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) || |
| 455 | (pd->ctlinterrupthandler != config->ctlinterrupthandler) || |
| 456 | (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) { |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 457 | printf("%s: FAIL\n", __func__); |
| 458 | hang(); |
| 459 | } else { |
| 460 | debug("%s: PASS\n", __func__); |
| 461 | } |
| 462 | } |
| 463 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 464 | void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss, |
| 465 | struct reginitdata *reginit_data) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 466 | { |
| 467 | int ret, i; |
| 468 | |
| 469 | ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data", |
| 470 | (u32 *)reginit_data->ctl_regs, |
| 471 | LPDDR4_INTR_CTL_REG_COUNT); |
| 472 | if (ret) |
| 473 | printf("Error reading ctrl data %d\n", ret); |
| 474 | |
| 475 | for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) |
| 476 | reginit_data->ctl_regs_offs[i] = i; |
| 477 | |
| 478 | ret = dev_read_u32_array(ddrss->dev, "ti,pi-data", |
| 479 | (u32 *)reginit_data->pi_regs, |
| 480 | LPDDR4_INTR_PHY_INDEP_REG_COUNT); |
| 481 | if (ret) |
| 482 | printf("Error reading PI data\n"); |
| 483 | |
| 484 | for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) |
| 485 | reginit_data->pi_regs_offs[i] = i; |
| 486 | |
| 487 | ret = dev_read_u32_array(ddrss->dev, "ti,phy-data", |
| 488 | (u32 *)reginit_data->phy_regs, |
| 489 | LPDDR4_INTR_PHY_REG_COUNT); |
| 490 | if (ret) |
| 491 | printf("Error reading PHY data %d\n", ret); |
| 492 | |
| 493 | for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++) |
| 494 | reginit_data->phy_regs_offs[i] = i; |
| 495 | } |
| 496 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 497 | void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 498 | { |
| 499 | u32 status = 0U; |
| 500 | struct reginitdata reginitdata; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 501 | lpddr4_obj *driverdt = ddrss->driverdt; |
| 502 | lpddr4_privatedata *pd = &ddrss->pd; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 503 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 504 | populate_data_array_from_dt(ddrss, ®initdata); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 505 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 506 | status = driverdt->writectlconfig(pd, reginitdata.ctl_regs, |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 507 | reginitdata.ctl_regs_offs, |
| 508 | LPDDR4_INTR_CTL_REG_COUNT); |
| 509 | if (!status) |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 510 | status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs, |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 511 | reginitdata.pi_regs_offs, |
| 512 | LPDDR4_INTR_PHY_INDEP_REG_COUNT); |
| 513 | if (!status) |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 514 | status = driverdt->writephyconfig(pd, reginitdata.phy_regs, |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 515 | reginitdata.phy_regs_offs, |
| 516 | LPDDR4_INTR_PHY_REG_COUNT); |
| 517 | if (status) { |
| 518 | printf("%s: FAIL\n", __func__); |
| 519 | hang(); |
| 520 | } |
| 521 | } |
| 522 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 523 | void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 524 | { |
| 525 | u32 status = 0U; |
| 526 | u32 regval = 0U; |
| 527 | u32 offset = 0U; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 528 | lpddr4_obj *driverdt = ddrss->driverdt; |
| 529 | lpddr4_privatedata *pd = &ddrss->pd; |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 530 | |
| 531 | TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset); |
| 532 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 533 | status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 534 | if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) { |
| 535 | printf("%s: Pre start FAIL\n", __func__); |
| 536 | hang(); |
| 537 | } |
| 538 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 539 | status = driverdt->start(pd); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 540 | if (status > 0U) { |
| 541 | printf("%s: FAIL\n", __func__); |
| 542 | hang(); |
| 543 | } |
| 544 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 545 | status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 546 | if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) { |
| 547 | printf("%s: Post start FAIL\n", __func__); |
| 548 | hang(); |
| 549 | } else { |
| 550 | debug("%s: Post start PASS\n", __func__); |
| 551 | } |
| 552 | } |
| 553 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 554 | static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) |
| 555 | { |
| 556 | writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); |
| 557 | writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); |
| 558 | } |
| 559 | |
| 560 | static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word) |
| 561 | { |
| 562 | int i; |
| 563 | |
| 564 | printf("ECC is enabled, priming DDR which will take several seconds.\n"); |
| 565 | |
| 566 | for (i = 0; i < (size / 4); i++) |
| 567 | addr[i] = word; |
| 568 | } |
| 569 | |
| 570 | static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) |
| 571 | { |
| 572 | fdtdec_setup_mem_size_base_lowest(); |
| 573 | |
| 574 | ddrss->ecc_reserved_space = gd->ram_size; |
| 575 | do_div(ddrss->ecc_reserved_space, 9); |
| 576 | |
| 577 | /* Round to clean number */ |
| 578 | ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space)); |
| 579 | } |
| 580 | |
| 581 | static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) |
| 582 | { |
| 583 | u32 ecc_region_start = ddrss->ecc_regions[0].start; |
| 584 | u32 ecc_range = ddrss->ecc_regions[0].range; |
| 585 | u32 base = (u32)ddrss->ddrss_ss_cfg; |
| 586 | u32 val; |
| 587 | |
| 588 | /* Only Program region 0 which covers full ddr space */ |
| 589 | k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); |
| 590 | |
| 591 | /* Enable ECC, RMW, WR_ALLOC */ |
| 592 | writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | |
| 593 | DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG); |
| 594 | |
| 595 | /* Preload ECC Mem region with 0's */ |
| 596 | k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range, |
| 597 | 0x00000000); |
| 598 | |
| 599 | /* Clear Error Count Register */ |
| 600 | writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); |
| 601 | |
| 602 | /* Enable ECC Check */ |
| 603 | val = readl(base + DDRSS_ECC_CTRL_REG); |
| 604 | val |= DDRSS_ECC_CTRL_REG_ECC_CK; |
| 605 | writel(val, base + DDRSS_ECC_CTRL_REG); |
| 606 | } |
| 607 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 608 | static int k3_ddrss_probe(struct udevice *dev) |
| 609 | { |
| 610 | int ret; |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 611 | struct k3_ddrss_desc *ddrss = dev_get_priv(dev); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 612 | |
| 613 | debug("%s(dev=%p)\n", __func__, dev); |
| 614 | |
| 615 | ret = k3_ddrss_ofdata_to_priv(dev); |
| 616 | if (ret) |
| 617 | return ret; |
| 618 | |
| 619 | ddrss->dev = dev; |
| 620 | ret = k3_ddrss_power_on(ddrss); |
| 621 | if (ret) |
| 622 | return ret; |
| 623 | |
Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame] | 624 | #ifdef CONFIG_K3_AM64_DDRSS |
Dominic Rath | 6feaf59 | 2022-04-06 11:56:47 +0200 | [diff] [blame] | 625 | /* AM64x supports only up to 2 GB SDRAM */ |
| 626 | writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); |
Dave Gerlach | 2c861a9 | 2021-05-11 10:22:12 -0500 | [diff] [blame] | 627 | writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); |
| 628 | #endif |
| 629 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 630 | ddrss->driverdt = lpddr4_getinstance(); |
| 631 | |
| 632 | k3_lpddr4_probe(ddrss); |
| 633 | k3_lpddr4_init(ddrss); |
| 634 | k3_lpddr4_hardware_reg_init(ddrss); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 635 | |
| 636 | ret = k3_ddrss_init_freq(ddrss); |
| 637 | if (ret) |
| 638 | return ret; |
| 639 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 640 | k3_lpddr4_start(ddrss); |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 641 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 642 | if (ddrss->ti_ecc_enabled) { |
| 643 | if (!ddrss->ddrss_ss_cfg) { |
| 644 | printf("%s: ss_cfg is required if ecc is enabled but not provided.", |
| 645 | __func__); |
| 646 | return -EINVAL; |
| 647 | } |
| 648 | |
| 649 | k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); |
| 650 | |
| 651 | /* Always configure one region that covers full DDR space */ |
| 652 | ddrss->ecc_regions[0].start = gd->ram_base; |
| 653 | ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; |
| 654 | k3_ddrss_lpddr4_ecc_init(ddrss); |
| 655 | } |
| 656 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 657 | return ret; |
| 658 | } |
| 659 | |
Dave Gerlach | 296c83a | 2022-03-17 12:03:43 -0500 | [diff] [blame] | 660 | int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) |
| 661 | { |
| 662 | struct k3_ddrss_desc *ddrss = dev_get_priv(dev); |
| 663 | u64 start[CONFIG_NR_DRAM_BANKS]; |
| 664 | u64 size[CONFIG_NR_DRAM_BANKS]; |
| 665 | int bank; |
| 666 | |
| 667 | if (ddrss->ecc_reserved_space == 0) |
| 668 | return 0; |
| 669 | |
| 670 | for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { |
| 671 | if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { |
| 672 | ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; |
| 673 | bd->bi_dram[bank].size = 0; |
| 674 | } else { |
| 675 | bd->bi_dram[bank].size -= ddrss->ecc_reserved_space; |
| 676 | break; |
| 677 | } |
| 678 | } |
| 679 | |
| 680 | for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { |
| 681 | start[bank] = bd->bi_dram[bank].start; |
| 682 | size[bank] = bd->bi_dram[bank].size; |
| 683 | } |
| 684 | |
| 685 | return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); |
| 686 | } |
| 687 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 688 | static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) |
| 689 | { |
| 690 | return 0; |
| 691 | } |
| 692 | |
| 693 | static struct ram_ops k3_ddrss_ops = { |
| 694 | .get_info = k3_ddrss_get_info, |
| 695 | }; |
| 696 | |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 697 | static const struct k3_ddrss_data k3_data = { |
| 698 | .flags = SINGLE_DDR_SUBSYSTEM, |
| 699 | }; |
| 700 | |
| 701 | static const struct k3_ddrss_data j721s2_data = { |
| 702 | .flags = MULTI_DDR_SUBSYSTEM, |
| 703 | }; |
| 704 | |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 705 | static const struct udevice_id k3_ddrss_ids[] = { |
Bryan Brattlof | debb045 | 2022-11-03 19:13:53 -0500 | [diff] [blame] | 706 | {.compatible = "ti,am62a-ddrss", .data = (ulong)&k3_data, }, |
Aswath Govindraju | b232cb4 | 2022-01-25 20:56:29 +0530 | [diff] [blame] | 707 | {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, }, |
| 708 | {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, }, |
| 709 | {.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, }, |
Dave Gerlach | d712b36 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 710 | {} |
| 711 | }; |
| 712 | |
| 713 | U_BOOT_DRIVER(k3_ddrss) = { |
| 714 | .name = "k3_ddrss", |
| 715 | .id = UCLASS_RAM, |
| 716 | .of_match = k3_ddrss_ids, |
| 717 | .ops = &k3_ddrss_ops, |
| 718 | .probe = k3_ddrss_probe, |
| 719 | .priv_auto = sizeof(struct k3_ddrss_desc), |
| 720 | }; |
Aswath Govindraju | 6324bc7 | 2022-01-25 20:56:30 +0530 | [diff] [blame] | 721 | |
| 722 | static int k3_msmc_set_config(struct k3_msmc *msmc) |
| 723 | { |
| 724 | u32 ddr_cfg0 = 0; |
| 725 | u32 ddr_cfg1 = 0; |
| 726 | |
| 727 | ddr_cfg0 |= msmc->gran << 24; |
| 728 | ddr_cfg0 |= msmc->size << 16; |
| 729 | /* heartbeat_per, bit[4:0] setting to 3 is advisable */ |
| 730 | ddr_cfg0 |= 3; |
| 731 | |
| 732 | /* Program MULTI_DDR_CFG0 */ |
| 733 | writel(ddr_cfg0, MULTI_DDR_CFG0); |
| 734 | |
| 735 | ddr_cfg1 |= msmc->enable << 16; |
| 736 | ddr_cfg1 |= msmc->config << 8; |
| 737 | ddr_cfg1 |= msmc->active; |
| 738 | |
| 739 | /* Program MULTI_DDR_CFG1 */ |
| 740 | writel(ddr_cfg1, MULTI_DDR_CFG1); |
| 741 | |
| 742 | /* Program DDR_CFG_LOAD */ |
| 743 | writel(0x60000000, DDR_CFG_LOAD); |
| 744 | |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | static int k3_msmc_probe(struct udevice *dev) |
| 749 | { |
| 750 | struct k3_msmc *msmc = dev_get_priv(dev); |
| 751 | int ret = 0; |
| 752 | |
| 753 | /* Read the granular size from DT */ |
| 754 | ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran); |
| 755 | if (ret) { |
| 756 | dev_err(dev, "missing intrlv-gran property"); |
| 757 | return -EINVAL; |
| 758 | } |
| 759 | |
| 760 | /* Read the interleave region from DT */ |
| 761 | ret = dev_read_u32(dev, "intrlv-size", &msmc->size); |
| 762 | if (ret) { |
| 763 | dev_err(dev, "missing intrlv-size property"); |
| 764 | return -EINVAL; |
| 765 | } |
| 766 | |
| 767 | /* Read ECC enable config */ |
| 768 | ret = dev_read_u32(dev, "ecc-enable", &msmc->enable); |
| 769 | if (ret) { |
| 770 | dev_err(dev, "missing ecc-enable property"); |
| 771 | return -EINVAL; |
| 772 | } |
| 773 | |
| 774 | /* Read EMIF configuration */ |
| 775 | ret = dev_read_u32(dev, "emif-config", &msmc->config); |
| 776 | if (ret) { |
| 777 | dev_err(dev, "missing emif-config property"); |
| 778 | return -EINVAL; |
| 779 | } |
| 780 | |
| 781 | /* Read EMIF active */ |
| 782 | ret = dev_read_u32(dev, "emif-active", &msmc->active); |
| 783 | if (ret) { |
| 784 | dev_err(dev, "missing emif-active property"); |
| 785 | return -EINVAL; |
| 786 | } |
| 787 | |
| 788 | ret = k3_msmc_set_config(msmc); |
| 789 | if (ret) { |
| 790 | dev_err(dev, "error setting msmc config"); |
| 791 | return -EINVAL; |
| 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | static const struct udevice_id k3_msmc_ids[] = { |
| 798 | { .compatible = "ti,j721s2-msmc"}, |
| 799 | {} |
| 800 | }; |
| 801 | |
| 802 | U_BOOT_DRIVER(k3_msmc) = { |
| 803 | .name = "k3_msmc", |
| 804 | .of_match = k3_msmc_ids, |
| 805 | .id = UCLASS_MISC, |
| 806 | .probe = k3_msmc_probe, |
| 807 | .priv_auto = sizeof(struct k3_msmc), |
| 808 | .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, |
| 809 | }; |