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git01.mediatek.com / filogic / uboot / d814ce2c5680b2a43795e21381978ea784ed9e32 / . / include / configs / sama5d3_xplained.h
blob: a10057452fe4d86a344e96263f0b3f739a2b5c96 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]2/*
3 * Configuration settings for the SAMA5D3 Xplained board.
4 *
5 * Copyright (C) 2014 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Fabien Lehoussel04df71a2020-02-24 16:45:31 +0100[diff] [blame]12#include <linux/sizes.h>
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]13#include "at91-sama5_common.h"
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]14
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]15/*
16 * This needs to be defined for the OHCI code to work but it is defined as
17 * ATMEL_ID_UHPHS in the CPU specific header files.
18 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]19#define ATMEL_ID_UHP 32
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]20
21/*
22 * Specify the clock enable bit in the PMC_SCER register.
23 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]24#define ATMEL_PMC_UHP (1 << 6)
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]25
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]26/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]27#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]28#define CONFIG_SYS_SDRAM_SIZE 0x10000000
29
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]30/* NAND flash */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]31#ifdef CONFIG_CMD_NAND
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]32#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]33#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]34/* our ALE is AD21 */
35#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
36/* our CLE is AD22 */
37#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]38#endif
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]39
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]40/* USB */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]41#ifdef CONFIG_CMD_USB
42#define CONFIG_USB_ATMEL
43#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
44#define CONFIG_USB_OHCI_NEW
45#define CONFIG_SYS_USB_OHCI_CPU_INIT
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]46#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]47#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
48#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]49#endif
50
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]51/* SPL */
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]52
Fabien Lehoussel04df71a2020-02-24 16:45:31 +0100[diff] [blame]53/* size of u-boot.bin to load */
54#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K)
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]55
Michael Opdenacker67226142021-05-31 23:23:48 +0200[diff] [blame]56/* Falcon boot support on raw MMC */
Michael Opdenacker67226142021-05-31 23:23:48 +0200[diff] [blame]57/* U-Boot proper stored by default at 0x200 (256 KiB) */
Michael Opdenacker67226142021-05-31 23:23:48 +0200[diff] [blame]58
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]59#endif