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git01.mediatek.com / filogic / uboot / d7cdf30730bcbd2859a4ff34488ca224a1715eb9 / . / arch / powerpc / include / asm / fsl_portals.h
blob: b1fd6bd5cef6613eb6a09a0a3158b0aed6122bd0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]2/*
Haiying Wangd38d4b22011-03-01 09:30:07 -0500[diff] [blame]3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]4 */
5
6#ifndef _FSL_PORTALS_H_
7#define _FSL_PORTALS_H_
8
9/* entries must be in order and contiguous */
10enum fsl_dpaa_dev {
11 FSL_HW_PORTAL_SEC,
12#ifdef CONFIG_SYS_DPAA_FMAN
13 FSL_HW_PORTAL_FMAN1,
14#if (CONFIG_SYS_NUM_FMAN == 2)
15 FSL_HW_PORTAL_FMAN2,
16#endif
17#endif
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]18 FSL_HW_PORTAL_PME,
Kumar Gala9d8e8132011-09-10 10:44:13 -0500[diff] [blame]19#ifdef CONFIG_SYS_FSL_RAID_ENGINE
20 FSL_HW_PORTAL_RAID_ENGINE,
21#endif
Kumar Gala4eb3c372011-10-14 13:28:52 -0500[diff] [blame]22#ifdef CONFIG_SYS_DPAA_RMAN
23 FSL_HW_PORTAL_RMAN,
24#endif
Andy Fleming81177ad2012-10-08 07:44:18 +0000[diff] [blame]25#ifdef CONFIG_SYS_DPAA_DCE
26 FSL_HW_PORTAL_DCE,
27#endif
Kumar Gala4eb3c372011-10-14 13:28:52 -0500[diff] [blame]28
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]29};
30
31struct qportal_info {
32 u16 dliodn; /* DQRR LIODN */
33 u16 fliodn; /* frame data LIODN */
34 u16 liodn_offset;
35 u8 sdest;
36};
37
38#define SET_QP_INFO(dqrr, fdata, off, dest) \
39 { .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
40
41extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
42 u32 *liodns, int liodn_offset);
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]43extern struct qportal_info qp_info[];
44extern void fdt_portal(void *blob, const char *compat, const char *container,
45 u64 addr, u32 size);
46
47#endif