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git01.mediatek.com / filogic / uboot / d7bca5d942079fa4522765789246d72c4881291d / . / board / micronas / vct / dcgu.c
blob: b2e86b72e610e6000a3a7ace29ef4108efe377a5 [file] [log] [blame]
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]1/*
2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
4 * Original Author Guenter Gebhardt
5 * Copyright (C) 2006 Micronas GmbH
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/errno.h>
25
26#include "vct.h"
27
28int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
29{
30 u32 enable;
31 union dcgu_clk_en1 en1;
32 union dcgu_clk_en2 en2;
33
34 switch (setup) {
35 case DCGU_SWITCH_ON:
36 enable = 1;
37 break;
38 case DCGU_SWITCH_OFF:
39 enable = 0;
40 break;
41 default:
42 printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
43 setup);
44 return -EINVAL;
45 }
46
47 if (module == DCGU_HW_MODULE_CPU)
48 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
49 else
50 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
51
52 switch (module) {
53 case DCGU_HW_MODULE_MSMC:
54 en1.bits.en_clkmsmc = enable;
55 break;
56 case DCGU_HW_MODULE_SSI_S:
57 en1.bits.en_clkssi_s = enable;
58 break;
59 case DCGU_HW_MODULE_SSI_M:
60 en1.bits.en_clkssi_m = enable;
61 break;
62 case DCGU_HW_MODULE_SMC:
63 en1.bits.en_clksmc = enable;
64 break;
65 case DCGU_HW_MODULE_EBI:
66 en1.bits.en_clkebi = enable;
67 break;
68 case DCGU_HW_MODULE_USB_PLL:
69 en1.bits.en_usbpll = enable;
70 break;
71 case DCGU_HW_MODULE_USB_60:
72 en1.bits.en_clkusb60 = enable;
73 break;
74 case DCGU_HW_MODULE_USB_24:
75 en1.bits.en_clkusb24 = enable;
76 break;
77 case DCGU_HW_MODULE_UART_2:
78 en1.bits.en_clkuart2 = enable;
79 break;
80 case DCGU_HW_MODULE_UART_1:
81 en1.bits.en_clkuart1 = enable;
82 break;
83 case DCGU_HW_MODULE_PERI:
84 en1.bits.en_clkperi20 = enable;
85 break;
86 case DCGU_HW_MODULE_CPU:
87 en2.bits.en_clkcpu = enable;
88 break;
89 case DCGU_HW_MODULE_I2S:
90 en1.bits.en_clk_i2s_dly = enable;
91 break;
92 case DCGU_HW_MODULE_ABP_SCC:
93 en1.bits.en_clk_scc_abp = enable;
94 break;
95 case DCGU_HW_MODULE_SPDIF:
96 en1.bits.en_clk_dtv_spdo = enable;
97 break;
98 case DCGU_HW_MODULE_AD:
99 en1.bits.en_clkad = enable;
100 break;
101 case DCGU_HW_MODULE_MVD:
102 en1.bits.en_clkmvd = enable;
103 break;
104 case DCGU_HW_MODULE_TSD:
105 en1.bits.en_clktsd = enable;
106 break;
107 case DCGU_HW_MODULE_GA:
108 en1.bits.en_clkga = enable;
109 break;
110 case DCGU_HW_MODULE_DVP:
111 en1.bits.en_clkdvp = enable;
112 break;
113 case DCGU_HW_MODULE_MR2:
114 en1.bits.en_clkmr2 = enable;
115 break;
116 case DCGU_HW_MODULE_MR1:
117 en1.bits.en_clkmr1 = enable;
118 break;
119 default:
120 printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
121 __LINE__, module);
122 return -EINVAL;
123 }
124
125 /*
126 * The reg_read() following the reg_write() below forces the write to
127 * be really done on the bus.
128 * Otherwise the clock may not be switched on when this API function
129 * returns, which may cause an bus error if a registers of the hardware
130 * module connected to the clock is accessed.
131 */
132 if (module == DCGU_HW_MODULE_CPU) {
133 reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
134 en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
135 } else {
136 reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
137 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
138 }
139
140 return 0;
141}
142
143int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
144{
145 union dcgu_reset_unit1 val;
146 u32 enable;
147
148 switch (setup) {
149 case DCGU_SWITCH_ON:
150 enable = 1;
151 break;
152 case DCGU_SWITCH_OFF:
153 enable = 0;
154 break;
155 default:
156 printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
157 setup);
158 return -EINVAL;
159 }
160
161 val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
162 switch (module) {
163 case DCGU_HW_MODULE_MSMC:
164 val.bits.swreset_clkmsmc = enable;
165 break;
166 case DCGU_HW_MODULE_SSI_S:
167 val.bits.swreset_clkssi_s = enable;
168 break;
169 case DCGU_HW_MODULE_SSI_M:
170 val.bits.swreset_clkssi_m = enable;
171 break;
172 case DCGU_HW_MODULE_SMC:
173 val.bits.swreset_clksmc = enable;
174 break;
175 case DCGU_HW_MODULE_EBI:
176 val.bits.swreset_clkebi = enable;
177 break;
178 case DCGU_HW_MODULE_USB_60:
179 val.bits.swreset_clkusb60 = enable;
180 break;
181 case DCGU_HW_MODULE_USB_24:
182 val.bits.swreset_clkusb24 = enable;
183 break;
184 case DCGU_HW_MODULE_UART_2:
185 val.bits.swreset_clkuart2 = enable;
186 break;
187 case DCGU_HW_MODULE_UART_1:
188 val.bits.swreset_clkuart1 = enable;
189 break;
190 case DCGU_HW_MODULE_PWM:
191 val.bits.swreset_pwm = enable;
192 break;
193 case DCGU_HW_MODULE_GPT:
194 val.bits.swreset_gpt = enable;
195 break;
196 case DCGU_HW_MODULE_I2C2:
197 val.bits.swreset_i2c2 = enable;
198 break;
199 case DCGU_HW_MODULE_I2C1:
200 val.bits.swreset_i2c1 = enable;
201 break;
202 case DCGU_HW_MODULE_GPIO2:
203 val.bits.swreset_gpio2 = enable;
204 break;
205 case DCGU_HW_MODULE_GPIO1:
206 val.bits.swreset_gpio1 = enable;
207 break;
208 case DCGU_HW_MODULE_CPU:
209 val.bits.swreset_clkcpu = enable;
210 break;
211 case DCGU_HW_MODULE_I2S:
212 val.bits.swreset_clk_i2s_dly = enable;
213 break;
214 case DCGU_HW_MODULE_ABP_SCC:
215 val.bits.swreset_clk_scc_abp = enable;
216 break;
217 case DCGU_HW_MODULE_SPDIF:
218 val.bits.swreset_clk_dtv_spdo = enable;
219 break;
220 case DCGU_HW_MODULE_AD:
221 val.bits.swreset_clkad = enable;
222 break;
223 case DCGU_HW_MODULE_MVD:
224 val.bits.swreset_clkmvd = enable;
225 break;
226 case DCGU_HW_MODULE_TSD:
227 val.bits.swreset_clktsd = enable;
228 break;
229 case DCGU_HW_MODULE_TSIO:
230 val.bits.swreset_clktsio = enable;
231 break;
232 case DCGU_HW_MODULE_GA:
233 val.bits.swreset_clkga = enable;
234 break;
235 case DCGU_HW_MODULE_MPC:
236 val.bits.swreset_clkmpc = enable;
237 break;
238 case DCGU_HW_MODULE_CVE:
239 val.bits.swreset_clkcve = enable;
240 break;
241 case DCGU_HW_MODULE_DVP:
242 val.bits.swreset_clkdvp = enable;
243 break;
244 case DCGU_HW_MODULE_MR2:
245 val.bits.swreset_clkmr2 = enable;
246 break;
247 case DCGU_HW_MODULE_MR1:
248 val.bits.swreset_clkmr1 = enable;
249 break;
250 default:
251 printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
252 __LINE__, module);
253 return -EINVAL;
254 }
255 reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
256
257 return 0;
258}