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git01.mediatek.com / filogic / uboot / d7bca5d942079fa4522765789246d72c4881291d / . / board / Marvell / mv88f6281gtw_ge / mv88f6281gtw_ge.c
blob: c959bf879e91c27b7acb88c5572392a5a70a9b2b [file] [log] [blame]
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]1/*
2 * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
3 *
4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 */
26
27#include <common.h>
28#include <netdev.h>
29#include <asm/arch/kirkwood.h>
30#include <asm/arch/mpp.h>
31#include "mv88f6281gtw_ge.h"
32
33DECLARE_GLOBAL_DATA_PTR;
34
35int board_init(void)
36{
37 /*
38 * default gpio configuration
39 * There are maximum 64 gpios controlled through 2 sets of registers
40 * the below configuration configures mainly initial LED status
41 */
42 kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
43 MV88F6281GTW_GE_OE_VAL_HIGH,
44 MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
45
46 /* Multi-Purpose Pins Functionality configuration */
47 u32 kwmpp_config[] = {
48 MPP0_SPI_SCn,
49 MPP1_SPI_MOSI,
50 MPP2_SPI_SCK,
51 MPP3_SPI_MISO,
52 MPP4_GPIO,
53 MPP5_GPO,
54 MPP6_SYSRST_OUTn,
55 MPP7_SPI_SCn,
56 MPP8_TW_SDA,
57 MPP9_TW_SCK,
58 MPP10_UART0_TXD,
59 MPP11_UART0_RXD,
60 MPP12_GPO,
61 MPP13_GPIO,
62 MPP14_GPIO,
63 MPP15_GPIO,
64 MPP16_GPIO,
65 MPP17_GPIO,
66 MPP18_GPO,
67 MPP19_GPO,
68 MPP20_GPIO,
69 MPP21_GPIO,
70 MPP22_GPIO,
71 MPP23_GPIO,
72 MPP24_GPIO,
73 MPP25_GPIO,
74 MPP26_GPIO,
75 MPP27_GPIO,
76 MPP28_GPIO,
77 MPP29_GPIO,
78 MPP30_GPIO,
79 MPP31_GPIO,
80 MPP32_GPIO,
81 MPP33_GPIO,
82 MPP34_GPIO,
83 MPP35_GPIO,
84 MPP36_GPIO,
85 MPP37_GPIO,
86 MPP38_GPIO,
87 MPP39_GPIO,
88 MPP40_GPIO,
89 MPP41_GPIO,
90 MPP42_GPIO,
91 MPP43_GPIO,
92 MPP44_GPIO,
93 MPP45_GPIO,
94 MPP46_GPIO,
95 MPP47_GPIO,
96 MPP48_GPIO,
97 MPP49_GPIO,
98 0
99 };
100 kirkwood_mpp_conf(kwmpp_config);
101
102 /*
103 * arch number of board
104 */
105 gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
106
107 /* adress of boot parameters */
108 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
109
110 return 0;
111}
112
113int dram_init(void)
114{
115 int i;
116
117 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
118 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
119 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
120 }
121 return 0;
122}
123
124#ifdef CONFIG_MV88E61XX_SWITCH
125void reset_phy(void)
126{
127 /* configure and initialize switch */
128 struct mv88e61xx_config swcfg = {
129 .name = "egiga0",
130 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
131 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
132 .led_init = MV88E61XX_LED_INIT_EN,
133 .mdip = MV88E61XX_MDIP_REVERSE,
134 .portstate = MV88E61XX_PORTSTT_FORWARDING,
135 .cpuport = (1 << 5),
136 .ports_enabled = 0x3f
137 };
138
139 mv88e61xx_switch_initialize(&swcfg);
140}
141#endif /* CONFIG_MV88E61XX_SWITCH */