Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d7b59322e8fc82d4516ffa7fef724ced04c9f812 / . / include / configs / db-88f6820-gp.h
blob: d378052a8f7caf0925ead9aded12df677b2ff853 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]2/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]4 */
5
6#ifndef _CONFIG_DB_88F6820_GP_H
7#define _CONFIG_DB_88F6820_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]12
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]13#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
14
15/*
16 * Commands configuration
17 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]18
19/* I2C */
20#define CONFIG_SYS_I2C
21#define CONFIG_SYS_I2C_MVTWSI
22#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
23#define CONFIG_SYS_I2C_SLAVE 0x0
24#define CONFIG_SYS_I2C_SPEED 100000
25
Konstantin Porotchkinc6cb8b72018-08-29 16:34:53 +0300[diff] [blame]26/*
27 * SPI Flash configuration for the environemnt access
28 */
Konstantin Porotchkinc6cb8b72018-08-29 16:34:53 +0300[diff] [blame]29
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]30/* SPI NOR flash default params, used by sf commands */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]31
Stefan Roese1746e872015-06-29 14:58:11 +0200[diff] [blame]32/*
33 * SDIO/MMC Card Configuration
34 */
Stefan Roese1746e872015-06-29 14:58:11 +0200[diff] [blame]35#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
36
Stefan Roese10aad202015-06-29 14:58:14 +0200[diff] [blame]37/*
38 * SATA/SCSI/AHCI configuration
39 */
Stefan Roese10aad202015-06-29 14:58:14 +0200[diff] [blame]40#define CONFIG_SCSI_AHCI_PLAT
41#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
42#define CONFIG_SYS_SCSI_MAX_LUN 1
43#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
44 CONFIG_SYS_SCSI_MAX_LUN)
45
Stefan Roese2feb2262015-06-29 14:58:16 +0200[diff] [blame]46/* USB/EHCI configuration */
Stefan Roese2feb2262015-06-29 14:58:16 +0200[diff] [blame]47#define CONFIG_EHCI_IS_TDI
48
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]49/* Environment in SPI NOR flash */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]50#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
51#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
52#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
53
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]54#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
55
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]56/* PCIe support */
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]57#ifndef CONFIG_SPL_BUILD
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]58#define CONFIG_PCI_SCAN_SHOW
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]59#endif
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]60
Kevin Smith2366bcc2015-05-18 16:09:46 +0000[diff] [blame]61/* Keep device tree and initrd in lower memory so the kernel can access them */
62#define CONFIG_EXTRA_ENV_SETTINGS \
63 "fdt_high=0x10000000\0" \
64 "initrd_high=0x10000000\0"
65
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]66/* SPL */
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]67/*
68 * Select the boot device here
69 *
70 * Currently supported are:
71 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
72 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
73 */
74#define SPL_BOOT_SPI_NOR_FLASH 1
75#define SPL_BOOT_SDIO_MMC_CARD 2
76#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
77
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]78/* Defines for SPL */
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]79#define CONFIG_SPL_SIZE (140 << 10)
80#define CONFIG_SPL_TEXT_BASE 0x40000030
81#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
82
83#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
84#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
85
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]86#ifdef CONFIG_SPL_BUILD
87#define CONFIG_SYS_MALLOC_SIMPLE
88#endif
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]89
90#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
91#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
92
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]93#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]94/* SPL related SPI defines */
Stefan Roese49e7d772015-11-20 13:51:57 +0100[diff] [blame]95#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]96#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
97#endif
98
99#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
100/* SPL related MMC defines */
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]101#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
102#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]103#ifdef CONFIG_SPL_BUILD
104#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
105#endif
106#endif
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]107
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]108/*
109 * mv-common.h should be defined after CMD configs since it used them
110 * to enable certain macros
111 */
112#include "mv-common.h"
113
114#endif /* _CONFIG_DB_88F6820_GP_H */