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git01.mediatek.com / filogic / uboot / d79de1d950d4779583a97be8eaab135d2bca3565 / . / drivers / net / davinci_emac.h
blob: 13cd68f040b931c811475086f4efc173ccbaf6a3 [file] [log] [blame]
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * Based on: mach-davinci/emac_defs.h
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame^]7 * SPDX-License-Identifier: GPL-2.0+
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]8 */
9
10#ifndef _DAVINCI_EMAC_H_
11#define _DAVINCI_EMAC_H_
12/* Ethernet Min/Max packet size */
13#define EMAC_MIN_ETHERNET_PKT_SIZE 60
14#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
Ilya Yanokff672762011-11-28 06:37:33 +0000[diff] [blame]15/* Buffer size (should be aligned on 32 byte and cache line) */
16#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
17 ARCH_DMA_MINALIGN)
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]18
19/* Number of RX packet buffers
20 * NOTE: Only 1 buffer supported as of now
21 */
22#define EMAC_MAX_RX_BUFFERS 10
23
24
25/***********************************************
26 ******** Internally used macros ***************
27 ***********************************************/
28
29#define EMAC_CH_TX 1
30#define EMAC_CH_RX 0
31
32/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
33 * reserve space for 64 descriptors max
34 */
35#define EMAC_RX_DESC_BASE 0x0
36#define EMAC_TX_DESC_BASE 0x1000
37
38/* EMAC Teardown value */
39#define EMAC_TEARDOWN_VALUE 0xfffffffc
40
41/* MII Status Register */
42#define MII_STATUS_REG 1
43
44/* Number of statistics registers */
45#define EMAC_NUM_STATS 36
46
47
48/* EMAC Descriptor */
49typedef volatile struct _emac_desc
50{
51 u_int32_t next; /* Pointer to next descriptor
52 in chain */
53 u_int8_t *buffer; /* Pointer to data buffer */
54 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
55 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
56} emac_desc;
57
58/* CPPI bit positions */
59#define EMAC_CPPI_SOP_BIT (0x80000000)
60#define EMAC_CPPI_EOP_BIT (0x40000000)
61#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
62#define EMAC_CPPI_EOQ_BIT (0x10000000)
63#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
64#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
65
66#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
67
68#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
69#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
70#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
71#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
72#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
73
74#define EMAC_MAC_ADDR_MATCH (1 << 19)
75#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
76
77#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
78#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
79
80
81#define MDIO_CONTROL_IDLE (0x80000000)
82#define MDIO_CONTROL_ENABLE (0x40000000)
83#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
84#define MDIO_CONTROL_FAULT (0x80000)
85#define MDIO_USERACCESS0_GO (0x80000000)
86#define MDIO_USERACCESS0_WRITE_READ (0x0)
87#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
88#define MDIO_USERACCESS0_ACK (0x20000000)
89
90/* Ethernet MAC Registers Structure */
91typedef struct {
92 dv_reg TXIDVER;
93 dv_reg TXCONTROL;
94 dv_reg TXTEARDOWN;
95 u_int8_t RSVD0[4];
96 dv_reg RXIDVER;
97 dv_reg RXCONTROL;
98 dv_reg RXTEARDOWN;
99 u_int8_t RSVD1[100];
100 dv_reg TXINTSTATRAW;
101 dv_reg TXINTSTATMASKED;
102 dv_reg TXINTMASKSET;
103 dv_reg TXINTMASKCLEAR;
104 dv_reg MACINVECTOR;
105 u_int8_t RSVD2[12];
106 dv_reg RXINTSTATRAW;
107 dv_reg RXINTSTATMASKED;
108 dv_reg RXINTMASKSET;
109 dv_reg RXINTMASKCLEAR;
110 dv_reg MACINTSTATRAW;
111 dv_reg MACINTSTATMASKED;
112 dv_reg MACINTMASKSET;
113 dv_reg MACINTMASKCLEAR;
114 u_int8_t RSVD3[64];
115 dv_reg RXMBPENABLE;
116 dv_reg RXUNICASTSET;
117 dv_reg RXUNICASTCLEAR;
118 dv_reg RXMAXLEN;
119 dv_reg RXBUFFEROFFSET;
120 dv_reg RXFILTERLOWTHRESH;
121 u_int8_t RSVD4[8];
122 dv_reg RX0FLOWTHRESH;
123 dv_reg RX1FLOWTHRESH;
124 dv_reg RX2FLOWTHRESH;
125 dv_reg RX3FLOWTHRESH;
126 dv_reg RX4FLOWTHRESH;
127 dv_reg RX5FLOWTHRESH;
128 dv_reg RX6FLOWTHRESH;
129 dv_reg RX7FLOWTHRESH;
130 dv_reg RX0FREEBUFFER;
131 dv_reg RX1FREEBUFFER;
132 dv_reg RX2FREEBUFFER;
133 dv_reg RX3FREEBUFFER;
134 dv_reg RX4FREEBUFFER;
135 dv_reg RX5FREEBUFFER;
136 dv_reg RX6FREEBUFFER;
137 dv_reg RX7FREEBUFFER;
138 dv_reg MACCONTROL;
139 dv_reg MACSTATUS;
140 dv_reg EMCONTROL;
141 dv_reg FIFOCONTROL;
142 dv_reg MACCONFIG;
143 dv_reg SOFTRESET;
144 u_int8_t RSVD5[88];
145 dv_reg MACSRCADDRLO;
146 dv_reg MACSRCADDRHI;
147 dv_reg MACHASH1;
148 dv_reg MACHASH2;
149 dv_reg BOFFTEST;
150 dv_reg TPACETEST;
151 dv_reg RXPAUSE;
152 dv_reg TXPAUSE;
153 u_int8_t RSVD6[16];
154 dv_reg RXGOODFRAMES;
155 dv_reg RXBCASTFRAMES;
156 dv_reg RXMCASTFRAMES;
157 dv_reg RXPAUSEFRAMES;
158 dv_reg RXCRCERRORS;
159 dv_reg RXALIGNCODEERRORS;
160 dv_reg RXOVERSIZED;
161 dv_reg RXJABBER;
162 dv_reg RXUNDERSIZED;
163 dv_reg RXFRAGMENTS;
164 dv_reg RXFILTERED;
165 dv_reg RXQOSFILTERED;
166 dv_reg RXOCTETS;
167 dv_reg TXGOODFRAMES;
168 dv_reg TXBCASTFRAMES;
169 dv_reg TXMCASTFRAMES;
170 dv_reg TXPAUSEFRAMES;
171 dv_reg TXDEFERRED;
172 dv_reg TXCOLLISION;
173 dv_reg TXSINGLECOLL;
174 dv_reg TXMULTICOLL;
175 dv_reg TXEXCESSIVECOLL;
176 dv_reg TXLATECOLL;
177 dv_reg TXUNDERRUN;
178 dv_reg TXCARRIERSENSE;
179 dv_reg TXOCTETS;
180 dv_reg FRAME64;
181 dv_reg FRAME65T127;
182 dv_reg FRAME128T255;
183 dv_reg FRAME256T511;
184 dv_reg FRAME512T1023;
185 dv_reg FRAME1024TUP;
186 dv_reg NETOCTETS;
187 dv_reg RXSOFOVERRUNS;
188 dv_reg RXMOFOVERRUNS;
189 dv_reg RXDMAOVERRUNS;
190 u_int8_t RSVD7[624];
191 dv_reg MACADDRLO;
192 dv_reg MACADDRHI;
193 dv_reg MACINDEX;
194 u_int8_t RSVD8[244];
195 dv_reg TX0HDP;
196 dv_reg TX1HDP;
197 dv_reg TX2HDP;
198 dv_reg TX3HDP;
199 dv_reg TX4HDP;
200 dv_reg TX5HDP;
201 dv_reg TX6HDP;
202 dv_reg TX7HDP;
203 dv_reg RX0HDP;
204 dv_reg RX1HDP;
205 dv_reg RX2HDP;
206 dv_reg RX3HDP;
207 dv_reg RX4HDP;
208 dv_reg RX5HDP;
209 dv_reg RX6HDP;
210 dv_reg RX7HDP;
211 dv_reg TX0CP;
212 dv_reg TX1CP;
213 dv_reg TX2CP;
214 dv_reg TX3CP;
215 dv_reg TX4CP;
216 dv_reg TX5CP;
217 dv_reg TX6CP;
218 dv_reg TX7CP;
219 dv_reg RX0CP;
220 dv_reg RX1CP;
221 dv_reg RX2CP;
222 dv_reg RX3CP;
223 dv_reg RX4CP;
224 dv_reg RX5CP;
225 dv_reg RX6CP;
226 dv_reg RX7CP;
227} emac_regs;
228
229/* EMAC Wrapper Registers Structure */
230typedef struct {
231#ifdef DAVINCI_EMAC_VERSION2
232 dv_reg idver;
233 dv_reg softrst;
234 dv_reg emctrl;
235 dv_reg c0rxthreshen;
236 dv_reg c0rxen;
237 dv_reg c0txen;
238 dv_reg c0miscen;
239 dv_reg c1rxthreshen;
240 dv_reg c1rxen;
241 dv_reg c1txen;
242 dv_reg c1miscen;
243 dv_reg c2rxthreshen;
244 dv_reg c2rxen;
245 dv_reg c2txen;
246 dv_reg c2miscen;
247 dv_reg c0rxthreshstat;
248 dv_reg c0rxstat;
249 dv_reg c0txstat;
250 dv_reg c0miscstat;
251 dv_reg c1rxthreshstat;
252 dv_reg c1rxstat;
253 dv_reg c1txstat;
254 dv_reg c1miscstat;
255 dv_reg c2rxthreshstat;
256 dv_reg c2rxstat;
257 dv_reg c2txstat;
258 dv_reg c2miscstat;
259 dv_reg c0rximax;
260 dv_reg c0tximax;
261 dv_reg c1rximax;
262 dv_reg c1tximax;
263 dv_reg c2rximax;
264 dv_reg c2tximax;
265#else
266 u_int8_t RSVD0[4100];
267 dv_reg EWCTL;
268 dv_reg EWINTTCNT;
269#endif
270} ewrap_regs;
271
272/* EMAC MDIO Registers Structure */
273typedef struct {
274 dv_reg VERSION;
275 dv_reg CONTROL;
276 dv_reg ALIVE;
277 dv_reg LINK;
278 dv_reg LINKINTRAW;
279 dv_reg LINKINTMASKED;
280 u_int8_t RSVD0[8];
281 dv_reg USERINTRAW;
282 dv_reg USERINTMASKED;
283 dv_reg USERINTMASKSET;
284 dv_reg USERINTMASKCLEAR;
285 u_int8_t RSVD1[80];
286 dv_reg USERACCESS0;
287 dv_reg USERPHYSEL0;
288 dv_reg USERACCESS1;
289 dv_reg USERPHYSEL1;
290} mdio_regs;
291
292int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
293int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
294
295typedef struct {
296 char name[64];
297 int (*init)(int phy_addr);
298 int (*is_phy_connected)(int phy_addr);
299 int (*get_link_speed)(int phy_addr);
300 int (*auto_negotiate)(int phy_addr);
301} phy_t;
302
303#endif /* _DAVINCI_EMAC_H_ */