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git01.mediatek.com / filogic / uboot / d79de1d950d4779583a97be8eaab135d2bca3565 / . / board / quantum / u-boot.lds.debug
blob: b2c562c33d9334e8391c6e98f3a3b9723c0dc585 [file] [log] [blame]
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame^]5 * SPDX-License-Identifier: GPL-2.0+
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]6 */
7
8OUTPUT_ARCH(powerpc)
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]9/* Do we need any of these for elf?
10 __DYNAMIC = 0; */
11SECTIONS
12{
13 /* Read-only sections, merged into text segment: */
14 . = + SIZEOF_HEADERS;
15 .interp : { *(.interp) }
16 .hash : { *(.hash) }
17 .dynsym : { *(.dynsym) }
18 .dynstr : { *(.dynstr) }
19 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]20 .rela.text : { *(.rela.text) }
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]21 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]22 .rela.data : { *(.rela.data) }
23 .rel.rodata : { *(.rel.rodata) }
24 .rela.rodata : { *(.rela.rodata) }
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]25 .rel.got : { *(.rel.got) }
26 .rela.got : { *(.rela.got) }
27 .rel.ctors : { *(.rel.ctors) }
28 .rela.ctors : { *(.rela.ctors) }
29 .rel.dtors : { *(.rel.dtors) }
30 .rela.dtors : { *(.rela.dtors) }
31 .rel.bss : { *(.rel.bss) }
32 .rela.bss : { *(.rela.bss) }
33 .rel.plt : { *(.rel.plt) }
34 .rela.plt : { *(.rela.plt) }
35 .init : { *(.init) }
36 .plt : { *(.plt) }
37 .text :
38 {
39 /* WARNING - the following is hand-optimized to fit within */
40 /* the sector layout of our flash chips! XXX FIXME XXX */
41
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]42 arch/powerpc/cpu/mpc8xx/start.o (.text)
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]43 common/dlmalloc.o (.text)
Peter Tyser685b7f52010-04-12 22:28:05 -0500[diff] [blame]44 lib/vsprintf.o (.text)
45 lib/crc32.o (.text)
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]46
47 . = env_offset;
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]48 common/env_embedded.o(.text)
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]49
50 *(.text)
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]51 *(.got1)
52 }
53 _etext = .;
54 PROVIDE (etext = .);
55 .rodata :
56 {
57 *(.rodata)
58 *(.rodata1)
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]59 *(.rodata.str1.4)
60 *(.eh_frame)
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]61 }
62 .fini : { *(.fini) } =0
63 .ctors : { *(.ctors) }
64 .dtors : { *(.dtors) }
65
66 /* Read-write section, merged into data segment: */
67 . = (. + 0x0FFF) & 0xFFFFF000;
68 _erotext = .;
69 PROVIDE (erotext = .);
70 .reloc :
71 {
72 *(.got)
73 _GOT2_TABLE_ = .;
74 *(.got2)
75 _FIXUP_TABLE_ = .;
76 *(.fixup)
77 }
78 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
79 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
80
81 .data :
82 {
83 *(.data)
84 *(.data1)
85 *(.sdata)
86 *(.sdata2)
87 *(.dynamic)
88 CONSTRUCTORS
89 }
90 _edata = .;
91 PROVIDE (edata = .);
92
93 __start___ex_table = .;
94 __ex_table : { *(__ex_table) }
95 __stop___ex_table = .;
96
97 . = ALIGN(4096);
98 __init_begin = .;
99 .text.init : { *(.text.init) }
100 .data.init : { *(.data.init) }
101 . = ALIGN(4096);
102 __init_end = .;
103
104 __bss_start = .;
105 .bss :
106 {
107 *(.sbss) *(.scommon)
108 *(.dynbss)
109 *(.bss)
110 *(COMMON)
111 }
Albert ARIBAUD0198f9d2013-03-30 00:19:53 +0000[diff] [blame]112 __bss_end = . ;
wdenk7d1eb822004-09-29 11:02:56 +0000[diff] [blame]113 PROVIDE (end = .);
114}