wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 6 | */ |
| 7 | #ifndef _PCI_PARTS_H_ |
| 8 | #define _PCI_PARTS_H_ |
| 9 | |
| 10 | |
| 11 | /* Board specific file containing: |
| 12 | * - PCI Memory Mapping |
| 13 | * - PCI IO Mapping |
| 14 | * - PCI Interrupt Mapping |
| 15 | */ |
| 16 | |
| 17 | /* PIP405 PCI INT Routing: |
| 18 | * IRQ0 VECTOR |
| 19 | * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31) |
| 20 | * VGA IDSEL = AD17 INTB# 29 |
| 21 | * SCSI IDSEL = AD18 INTC# 30 |
| 22 | * PC104 IDSEL0 = AD20 INTA# 28 |
| 23 | * PC104 IDSEL1 = AD21 INTB# 29 |
| 24 | * PC104 IDSEL2 = AD22 INTC# 30 |
| 25 | * PC104 IDSEL3 = AD23 INTD# 31 |
| 26 | * |
| 27 | * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00 |
| 28 | * ^ ^ ^ ^ ^ |
| 29 | * 31 23 15 10 7 |
| 30 | * E = Enabled |
| 31 | * B = Bussnumber |
| 32 | * D = Devicenumber (Device0 = AD10) |
| 33 | * F = Functionnumber |
| 34 | * R = Registernumber |
| 35 | * |
| 36 | * Device = (busdevfunc>>11) + 10 |
| 37 | * Vector = devicenumber % 4 + 28 |
| 38 | * |
| 39 | */ |
| 40 | #define PCI_HIGHEST_ON_BOARD_ID 19 |
| 41 | /*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */ |
| 42 | #define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28 |
| 43 | |
| 44 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 45 | /* PCI Device List for PIP405 */ |
| 46 | |
| 47 | /* Mapping: |
| 48 | * +-------------+------------+------------+--------------------------------+ |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 49 | * | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 50 | * +-------------+------------+------------+--------------------------------+ |
| 51 | * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) | |
| 52 | * | 0x00FFFFFF | | 0xA0FFFFFF | | |
| 53 | * +-------------+------------+------------+--------------------------------+ |
| 54 | * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) | |
| 55 | * | | 0x0000FFFF | 0xE800FFFF | | |
| 56 | * +-------------+------------+------------+--------------------------------+ |
| 57 | * | 0x80000000 | | 0x80000000 | VGA Controller Memory | |
| 58 | * | 0x80FFFFFF | | 0x80FFFFFF | | |
| 59 | * +-------------+------------+------------+--------------------------------+ |
| 60 | * | 0x81000000 | | 0x81000000 | SCSI Controller Memory | |
| 61 | * | 0x81FFFFFF | | 0x81FFFFFF | | |
| 62 | * +-------------+------------+------------+--------------------------------+ |
| 63 | */ |
| 64 | |
| 65 | struct pci_pip405_config_entry { |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 66 | int index; /* address */ |
| 67 | unsigned long val; /* value */ |
| 68 | int width; /* data size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 69 | }; |
| 70 | |
| 71 | extern void pci_pip405_write_regs(struct pci_controller *, |
| 72 | pci_dev_t, |
| 73 | struct pci_config_table *); |
| 74 | |
| 75 | /* PIIX4 ISA Bridge Function 0 */ |
| 76 | static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = { |
| 77 | {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */ |
wdenk | 2c9b05d | 2003-09-10 22:30:53 +0000 | [diff] [blame] | 78 | {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 79 | {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */ |
| 80 | {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 81 | {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 82 | #if defined(CONFIG_PIP405) |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 83 | {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */ |
| 84 | {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 85 | #endif |
| 86 | {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 87 | { } /* end of device table */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | /* PIIX4 IDE Controller Function 1 */ |
| 91 | static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = { |
wdenk | 2c9b05d | 2003-09-10 22:30:53 +0000 | [diff] [blame] | 92 | {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 93 | {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ |
wdenk | e39c284 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 94 | #if !defined(CONFIG_MIP405T) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 95 | {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */ |
wdenk | e39c284 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 96 | #else |
wdenk | 874ac26 | 2003-07-24 23:38:38 +0000 | [diff] [blame] | 97 | {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */ |
wdenk | e39c284 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 98 | #endif |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 99 | { } /* end of device table */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | /* PIIX4 USB Controller Function 2 */ |
| 103 | static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = { |
wdenk | e39c284 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 104 | #if !defined(CONFIG_MIP405T) |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 105 | {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 106 | {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 107 | {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ |
| 108 | {0xC0, 0x2000, 2}, /* Legacy support */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 109 | {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */ |
wdenk | e39c284 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 110 | #endif |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 111 | { } /* end of device table */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 112 | }; |
| 113 | |
| 114 | /* PIIX4 Power Management Function 3 */ |
| 115 | static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = { |
wdenk | 2c9b05d | 2003-09-10 22:30:53 +0000 | [diff] [blame] | 116 | {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 117 | {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */ |
wdenk | 2c9b05d | 2003-09-10 22:30:53 +0000 | [diff] [blame] | 118 | {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 119 | {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ |
| 120 | { } /* end of device table */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 121 | }; |
| 122 | /* PPC405 Dummy only used to prevent autosetup on this host bridge */ |
Wolfgang Denk | 0ee7077 | 2005-09-23 11:05:55 +0200 | [diff] [blame] | 123 | static struct pci_pip405_config_entry ppc405_dummy[] = { |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 124 | { } /* end of device table */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 125 | }; |
| 126 | |
| 127 | void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, |
| 128 | struct pci_config_table *entry); |
| 129 | |
| 130 | |
| 131 | static struct pci_config_table pci_pip405_config_table[]={ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 132 | {PCI_VENDOR_ID_IBM, /* 405 dummy */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 133 | PCI_DEVICE_ID_IBM_405GP, |
| 134 | PCI_ANY_ID, |
| 135 | PCI_ANY_ID, PCI_ANY_ID, 0, |
Wolfgang Denk | 0ee7077 | 2005-09-23 11:05:55 +0200 | [diff] [blame] | 136 | pci_pip405_write_regs, {(unsigned long) ppc405_dummy}}, |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 137 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 138 | {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 139 | PCI_DEVICE_ID_INTEL_82371AB_0, |
| 140 | PCI_ANY_ID, |
| 141 | PCI_ANY_ID, PCI_ANY_ID, 0, |
| 142 | pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}}, |
| 143 | |
| 144 | {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */ |
| 145 | PCI_DEVICE_ID_INTEL_82371AB, |
| 146 | PCI_ANY_ID, |
| 147 | PCI_ANY_ID, PCI_ANY_ID, 1, |
| 148 | pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}}, |
| 149 | |
| 150 | {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */ |
| 151 | PCI_DEVICE_ID_INTEL_82371AB_2, |
| 152 | PCI_ANY_ID, |
| 153 | PCI_ANY_ID, PCI_ANY_ID, 2, |
| 154 | pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}}, |
| 155 | |
| 156 | {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */ |
| 157 | PCI_DEVICE_ID_INTEL_82371AB_3, |
| 158 | PCI_ANY_ID, |
| 159 | PCI_ANY_ID, PCI_ANY_ID, 3, |
| 160 | pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}}, |
| 161 | |
| 162 | {PCI_ANY_ID, |
| 163 | PCI_ANY_ID, |
| 164 | PCI_CLASS_DISPLAY_VGA, |
| 165 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 166 | pci_405gp_setup_vga}, |
| 167 | |
| 168 | {PCI_ANY_ID, |
| 169 | PCI_ANY_ID, |
| 170 | PCI_CLASS_NOT_DEFINED_VGA, |
| 171 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 172 | pci_405gp_setup_vga}, |
| 173 | |
| 174 | { } |
| 175 | }; |
| 176 | #endif /* _PCI_PARTS_H_ */ |