blob: 7fe4ae74ea03b736a69500bc2da30a15e01f33f5 [file] [log] [blame]
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00005 */
6
7#include <common.h>
8#include <asm/processor.h>
9#include <asm/mmu.h>
10#include <asm/cache.h>
11#include <asm/immap_85xx.h>
12#include <asm/io.h>
13#include <miiphy.h>
14#include <libfdt.h>
15#include <fdt_support.h>
16#include <fsl_mdio.h>
17#include <tsec.h>
18#include <netdev.h>
19
20
21DECLARE_GLOBAL_DATA_PTR;
22
23int board_early_init_f(void)
24{
25 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
26
27 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
28 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
29
30 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
31 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
32 MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
33 setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
34 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
35 MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
36 MPC85xx_PMUXCR_IFC_AD_GPIO |
37 MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
38
39 return 0;
40}
41
42int checkboard(void)
43{
44 struct cpu_type *cpu;
45
Simon Glassa8b57392012-12-13 20:48:48 +000046 cpu = gd->arch.cpu;
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000047 printf("Board: %sRDB\n", cpu->name);
48
49 return 0;
50}
51
52#if defined(CONFIG_OF_BOARD_SETUP)
53void ft_board_setup(void *blob, bd_t *bd)
54{
55 phys_addr_t base;
56 phys_size_t size;
57
58 ft_cpu_setup(blob, bd);
59
60 base = getenv_bootm_low();
61 size = getenv_bootm_size();
62
63 fdt_fixup_memory(blob, (u64)base, (u64)size);
64
65 fdt_fixup_dr_usb(blob, bd);
66}
67#endif