Graeme Russ | a0190bd | 2012-12-02 04:55:11 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Taken from the linux kernel file of the same name |
| 3 | * |
| 4 | * (C) Copyright 2012 |
| 5 | * Graeme Russ, <graeme.russ@gmail.com> |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Graeme Russ | a0190bd | 2012-12-02 04:55:11 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _ASM_X86_MSR_INDEX_H |
| 11 | #define _ASM_X86_MSR_INDEX_H |
| 12 | |
| 13 | /* CPU model specific register (MSR) numbers */ |
| 14 | |
| 15 | /* x86-64 specific MSRs */ |
| 16 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
| 17 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
| 18 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
| 19 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
| 20 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
| 21 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
| 22 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
| 23 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
| 24 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
| 25 | |
| 26 | /* EFER bits: */ |
| 27 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
| 28 | #define _EFER_LME 8 /* Long mode enable */ |
| 29 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
| 30 | #define _EFER_NX 11 /* No execute enable */ |
| 31 | #define _EFER_SVME 12 /* Enable virtualization */ |
| 32 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
| 33 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
| 34 | |
| 35 | #define EFER_SCE (1<<_EFER_SCE) |
| 36 | #define EFER_LME (1<<_EFER_LME) |
| 37 | #define EFER_LMA (1<<_EFER_LMA) |
| 38 | #define EFER_NX (1<<_EFER_NX) |
| 39 | #define EFER_SVME (1<<_EFER_SVME) |
| 40 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
| 41 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
| 42 | |
| 43 | /* Intel MSRs. Some also available on other CPUs */ |
| 44 | #define MSR_IA32_PERFCTR0 0x000000c1 |
| 45 | #define MSR_IA32_PERFCTR1 0x000000c2 |
| 46 | #define MSR_FSB_FREQ 0x000000cd |
| 47 | |
| 48 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
| 49 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
| 50 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
| 51 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
| 52 | |
| 53 | #define MSR_MTRRcap 0x000000fe |
| 54 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
| 55 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
| 56 | |
| 57 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
| 58 | #define MSR_IA32_SYSENTER_ESP 0x00000175 |
| 59 | #define MSR_IA32_SYSENTER_EIP 0x00000176 |
| 60 | |
| 61 | #define MSR_IA32_MCG_CAP 0x00000179 |
| 62 | #define MSR_IA32_MCG_STATUS 0x0000017a |
| 63 | #define MSR_IA32_MCG_CTL 0x0000017b |
| 64 | |
| 65 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
| 66 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
| 67 | |
| 68 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
| 69 | #define MSR_IA32_DS_AREA 0x00000600 |
| 70 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
| 71 | |
| 72 | #define MSR_MTRRfix64K_00000 0x00000250 |
| 73 | #define MSR_MTRRfix16K_80000 0x00000258 |
| 74 | #define MSR_MTRRfix16K_A0000 0x00000259 |
| 75 | #define MSR_MTRRfix4K_C0000 0x00000268 |
| 76 | #define MSR_MTRRfix4K_C8000 0x00000269 |
| 77 | #define MSR_MTRRfix4K_D0000 0x0000026a |
| 78 | #define MSR_MTRRfix4K_D8000 0x0000026b |
| 79 | #define MSR_MTRRfix4K_E0000 0x0000026c |
| 80 | #define MSR_MTRRfix4K_E8000 0x0000026d |
| 81 | #define MSR_MTRRfix4K_F0000 0x0000026e |
| 82 | #define MSR_MTRRfix4K_F8000 0x0000026f |
| 83 | #define MSR_MTRRdefType 0x000002ff |
| 84 | |
| 85 | #define MSR_IA32_CR_PAT 0x00000277 |
| 86 | |
| 87 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
| 88 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
| 89 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
| 90 | #define MSR_IA32_LASTINTFROMIP 0x000001dd |
| 91 | #define MSR_IA32_LASTINTTOIP 0x000001de |
| 92 | |
| 93 | /* DEBUGCTLMSR bits (others vary by model): */ |
| 94 | #define DEBUGCTLMSR_LBR (1UL << 0) |
| 95 | #define DEBUGCTLMSR_BTF (1UL << 1) |
| 96 | #define DEBUGCTLMSR_TR (1UL << 6) |
| 97 | #define DEBUGCTLMSR_BTS (1UL << 7) |
| 98 | #define DEBUGCTLMSR_BTINT (1UL << 8) |
| 99 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
| 100 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
| 101 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
| 102 | |
| 103 | #define MSR_IA32_MC0_CTL 0x00000400 |
| 104 | #define MSR_IA32_MC0_STATUS 0x00000401 |
| 105 | #define MSR_IA32_MC0_ADDR 0x00000402 |
| 106 | #define MSR_IA32_MC0_MISC 0x00000403 |
| 107 | |
| 108 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
| 109 | |
| 110 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
| 111 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
| 112 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
| 113 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
| 114 | |
| 115 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
| 116 | |
| 117 | /* These are consecutive and not in the normal 4er MCE bank block */ |
| 118 | #define MSR_IA32_MC0_CTL2 0x00000280 |
| 119 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
| 120 | |
| 121 | #define MSR_P6_PERFCTR0 0x000000c1 |
| 122 | #define MSR_P6_PERFCTR1 0x000000c2 |
| 123 | #define MSR_P6_EVNTSEL0 0x00000186 |
| 124 | #define MSR_P6_EVNTSEL1 0x00000187 |
| 125 | |
| 126 | /* AMD64 MSRs. Not complete. See the architecture manual for a more |
| 127 | complete list. */ |
| 128 | |
| 129 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
| 130 | #define MSR_AMD64_NB_CFG 0xc001001f |
| 131 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
| 132 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
| 133 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
| 134 | #define MSR_AMD64_DC_CFG 0xc0011022 |
| 135 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
| 136 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
| 137 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
| 138 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
| 139 | #define MSR_AMD64_IBSOPRIP 0xc0011034 |
| 140 | #define MSR_AMD64_IBSOPDATA 0xc0011035 |
| 141 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
| 142 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
| 143 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
| 144 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
| 145 | #define MSR_AMD64_IBSCTL 0xc001103a |
| 146 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
| 147 | |
| 148 | /* Fam 15h MSRs */ |
| 149 | #define MSR_F15H_PERF_CTL 0xc0010200 |
| 150 | #define MSR_F15H_PERF_CTR 0xc0010201 |
| 151 | |
| 152 | /* Fam 10h MSRs */ |
| 153 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
| 154 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
| 155 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
| 156 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
| 157 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
| 158 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
| 159 | #define MSR_FAM10H_NODE_ID 0xc001100c |
| 160 | |
| 161 | /* K8 MSRs */ |
| 162 | #define MSR_K8_TOP_MEM1 0xc001001a |
| 163 | #define MSR_K8_TOP_MEM2 0xc001001d |
| 164 | #define MSR_K8_SYSCFG 0xc0010010 |
| 165 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
| 166 | /* C1E active bits in int pending message */ |
| 167 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
| 168 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
| 169 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
| 170 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
| 171 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
| 172 | |
| 173 | /* K7 MSRs */ |
| 174 | #define MSR_K7_EVNTSEL0 0xc0010000 |
| 175 | #define MSR_K7_PERFCTR0 0xc0010004 |
| 176 | #define MSR_K7_EVNTSEL1 0xc0010001 |
| 177 | #define MSR_K7_PERFCTR1 0xc0010005 |
| 178 | #define MSR_K7_EVNTSEL2 0xc0010002 |
| 179 | #define MSR_K7_PERFCTR2 0xc0010006 |
| 180 | #define MSR_K7_EVNTSEL3 0xc0010003 |
| 181 | #define MSR_K7_PERFCTR3 0xc0010007 |
| 182 | #define MSR_K7_CLK_CTL 0xc001001b |
| 183 | #define MSR_K7_HWCR 0xc0010015 |
| 184 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
| 185 | #define MSR_K7_FID_VID_STATUS 0xc0010042 |
| 186 | |
| 187 | /* K6 MSRs */ |
| 188 | #define MSR_K6_WHCR 0xc0000082 |
| 189 | #define MSR_K6_UWCCR 0xc0000085 |
| 190 | #define MSR_K6_EPMR 0xc0000086 |
| 191 | #define MSR_K6_PSOR 0xc0000087 |
| 192 | #define MSR_K6_PFIR 0xc0000088 |
| 193 | |
| 194 | /* Centaur-Hauls/IDT defined MSRs. */ |
| 195 | #define MSR_IDT_FCR1 0x00000107 |
| 196 | #define MSR_IDT_FCR2 0x00000108 |
| 197 | #define MSR_IDT_FCR3 0x00000109 |
| 198 | #define MSR_IDT_FCR4 0x0000010a |
| 199 | |
| 200 | #define MSR_IDT_MCR0 0x00000110 |
| 201 | #define MSR_IDT_MCR1 0x00000111 |
| 202 | #define MSR_IDT_MCR2 0x00000112 |
| 203 | #define MSR_IDT_MCR3 0x00000113 |
| 204 | #define MSR_IDT_MCR4 0x00000114 |
| 205 | #define MSR_IDT_MCR5 0x00000115 |
| 206 | #define MSR_IDT_MCR6 0x00000116 |
| 207 | #define MSR_IDT_MCR7 0x00000117 |
| 208 | #define MSR_IDT_MCR_CTRL 0x00000120 |
| 209 | |
| 210 | /* VIA Cyrix defined MSRs*/ |
| 211 | #define MSR_VIA_FCR 0x00001107 |
| 212 | #define MSR_VIA_LONGHAUL 0x0000110a |
| 213 | #define MSR_VIA_RNG 0x0000110b |
| 214 | #define MSR_VIA_BCR2 0x00001147 |
| 215 | |
| 216 | /* Transmeta defined MSRs */ |
| 217 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
| 218 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
| 219 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
| 220 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
| 221 | |
| 222 | /* Intel defined MSRs. */ |
| 223 | #define MSR_IA32_P5_MC_ADDR 0x00000000 |
| 224 | #define MSR_IA32_P5_MC_TYPE 0x00000001 |
| 225 | #define MSR_IA32_TSC 0x00000010 |
| 226 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
| 227 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
| 228 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
| 229 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
| 230 | |
| 231 | #define FEATURE_CONTROL_LOCKED (1<<0) |
| 232 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) |
| 233 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
| 234 | |
| 235 | #define MSR_IA32_APICBASE 0x0000001b |
| 236 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| 237 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
| 238 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
| 239 | |
| 240 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
| 241 | #define MSR_IA32_UCODE_REV 0x0000008b |
| 242 | |
| 243 | #define MSR_IA32_PERF_STATUS 0x00000198 |
| 244 | #define MSR_IA32_PERF_CTL 0x00000199 |
| 245 | |
| 246 | #define MSR_IA32_MPERF 0x000000e7 |
| 247 | #define MSR_IA32_APERF 0x000000e8 |
| 248 | |
| 249 | #define MSR_IA32_THERM_CONTROL 0x0000019a |
| 250 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
| 251 | |
| 252 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
| 253 | #define THERM_INT_LOW_ENABLE (1 << 1) |
| 254 | #define THERM_INT_PLN_ENABLE (1 << 24) |
| 255 | |
| 256 | #define MSR_IA32_THERM_STATUS 0x0000019c |
| 257 | |
| 258 | #define THERM_STATUS_PROCHOT (1 << 0) |
| 259 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
| 260 | |
| 261 | #define MSR_THERM2_CTL 0x0000019d |
| 262 | |
| 263 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
| 264 | |
| 265 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
| 266 | |
| 267 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
| 268 | |
| 269 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
| 270 | |
| 271 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
| 272 | |
| 273 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
| 274 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
| 275 | |
| 276 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
| 277 | |
| 278 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
| 279 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
| 280 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
| 281 | |
| 282 | /* Thermal Thresholds Support */ |
| 283 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
| 284 | #define THERM_SHIFT_THRESHOLD0 8 |
| 285 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
| 286 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
| 287 | #define THERM_SHIFT_THRESHOLD1 16 |
| 288 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
| 289 | #define THERM_STATUS_THRESHOLD0 (1 << 6) |
| 290 | #define THERM_LOG_THRESHOLD0 (1 << 7) |
| 291 | #define THERM_STATUS_THRESHOLD1 (1 << 8) |
| 292 | #define THERM_LOG_THRESHOLD1 (1 << 9) |
| 293 | |
| 294 | /* MISC_ENABLE bits: architectural */ |
| 295 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) |
| 296 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) |
| 297 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) |
| 298 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) |
| 299 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) |
| 300 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) |
| 301 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) |
| 302 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) |
| 303 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) |
| 304 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) |
| 305 | |
| 306 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ |
| 307 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) |
| 308 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) |
| 309 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) |
| 310 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) |
| 311 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) |
| 312 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) |
| 313 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) |
| 314 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) |
| 315 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) |
| 316 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) |
| 317 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) |
| 318 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) |
| 319 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) |
| 320 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) |
| 321 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) |
| 322 | |
| 323 | /* P4/Xeon+ specific */ |
| 324 | #define MSR_IA32_MCG_EAX 0x00000180 |
| 325 | #define MSR_IA32_MCG_EBX 0x00000181 |
| 326 | #define MSR_IA32_MCG_ECX 0x00000182 |
| 327 | #define MSR_IA32_MCG_EDX 0x00000183 |
| 328 | #define MSR_IA32_MCG_ESI 0x00000184 |
| 329 | #define MSR_IA32_MCG_EDI 0x00000185 |
| 330 | #define MSR_IA32_MCG_EBP 0x00000186 |
| 331 | #define MSR_IA32_MCG_ESP 0x00000187 |
| 332 | #define MSR_IA32_MCG_EFLAGS 0x00000188 |
| 333 | #define MSR_IA32_MCG_EIP 0x00000189 |
| 334 | #define MSR_IA32_MCG_RESERVED 0x0000018a |
| 335 | |
| 336 | /* Pentium IV performance counter MSRs */ |
| 337 | #define MSR_P4_BPU_PERFCTR0 0x00000300 |
| 338 | #define MSR_P4_BPU_PERFCTR1 0x00000301 |
| 339 | #define MSR_P4_BPU_PERFCTR2 0x00000302 |
| 340 | #define MSR_P4_BPU_PERFCTR3 0x00000303 |
| 341 | #define MSR_P4_MS_PERFCTR0 0x00000304 |
| 342 | #define MSR_P4_MS_PERFCTR1 0x00000305 |
| 343 | #define MSR_P4_MS_PERFCTR2 0x00000306 |
| 344 | #define MSR_P4_MS_PERFCTR3 0x00000307 |
| 345 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
| 346 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
| 347 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
| 348 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
| 349 | #define MSR_P4_IQ_PERFCTR0 0x0000030c |
| 350 | #define MSR_P4_IQ_PERFCTR1 0x0000030d |
| 351 | #define MSR_P4_IQ_PERFCTR2 0x0000030e |
| 352 | #define MSR_P4_IQ_PERFCTR3 0x0000030f |
| 353 | #define MSR_P4_IQ_PERFCTR4 0x00000310 |
| 354 | #define MSR_P4_IQ_PERFCTR5 0x00000311 |
| 355 | #define MSR_P4_BPU_CCCR0 0x00000360 |
| 356 | #define MSR_P4_BPU_CCCR1 0x00000361 |
| 357 | #define MSR_P4_BPU_CCCR2 0x00000362 |
| 358 | #define MSR_P4_BPU_CCCR3 0x00000363 |
| 359 | #define MSR_P4_MS_CCCR0 0x00000364 |
| 360 | #define MSR_P4_MS_CCCR1 0x00000365 |
| 361 | #define MSR_P4_MS_CCCR2 0x00000366 |
| 362 | #define MSR_P4_MS_CCCR3 0x00000367 |
| 363 | #define MSR_P4_FLAME_CCCR0 0x00000368 |
| 364 | #define MSR_P4_FLAME_CCCR1 0x00000369 |
| 365 | #define MSR_P4_FLAME_CCCR2 0x0000036a |
| 366 | #define MSR_P4_FLAME_CCCR3 0x0000036b |
| 367 | #define MSR_P4_IQ_CCCR0 0x0000036c |
| 368 | #define MSR_P4_IQ_CCCR1 0x0000036d |
| 369 | #define MSR_P4_IQ_CCCR2 0x0000036e |
| 370 | #define MSR_P4_IQ_CCCR3 0x0000036f |
| 371 | #define MSR_P4_IQ_CCCR4 0x00000370 |
| 372 | #define MSR_P4_IQ_CCCR5 0x00000371 |
| 373 | #define MSR_P4_ALF_ESCR0 0x000003ca |
| 374 | #define MSR_P4_ALF_ESCR1 0x000003cb |
| 375 | #define MSR_P4_BPU_ESCR0 0x000003b2 |
| 376 | #define MSR_P4_BPU_ESCR1 0x000003b3 |
| 377 | #define MSR_P4_BSU_ESCR0 0x000003a0 |
| 378 | #define MSR_P4_BSU_ESCR1 0x000003a1 |
| 379 | #define MSR_P4_CRU_ESCR0 0x000003b8 |
| 380 | #define MSR_P4_CRU_ESCR1 0x000003b9 |
| 381 | #define MSR_P4_CRU_ESCR2 0x000003cc |
| 382 | #define MSR_P4_CRU_ESCR3 0x000003cd |
| 383 | #define MSR_P4_CRU_ESCR4 0x000003e0 |
| 384 | #define MSR_P4_CRU_ESCR5 0x000003e1 |
| 385 | #define MSR_P4_DAC_ESCR0 0x000003a8 |
| 386 | #define MSR_P4_DAC_ESCR1 0x000003a9 |
| 387 | #define MSR_P4_FIRM_ESCR0 0x000003a4 |
| 388 | #define MSR_P4_FIRM_ESCR1 0x000003a5 |
| 389 | #define MSR_P4_FLAME_ESCR0 0x000003a6 |
| 390 | #define MSR_P4_FLAME_ESCR1 0x000003a7 |
| 391 | #define MSR_P4_FSB_ESCR0 0x000003a2 |
| 392 | #define MSR_P4_FSB_ESCR1 0x000003a3 |
| 393 | #define MSR_P4_IQ_ESCR0 0x000003ba |
| 394 | #define MSR_P4_IQ_ESCR1 0x000003bb |
| 395 | #define MSR_P4_IS_ESCR0 0x000003b4 |
| 396 | #define MSR_P4_IS_ESCR1 0x000003b5 |
| 397 | #define MSR_P4_ITLB_ESCR0 0x000003b6 |
| 398 | #define MSR_P4_ITLB_ESCR1 0x000003b7 |
| 399 | #define MSR_P4_IX_ESCR0 0x000003c8 |
| 400 | #define MSR_P4_IX_ESCR1 0x000003c9 |
| 401 | #define MSR_P4_MOB_ESCR0 0x000003aa |
| 402 | #define MSR_P4_MOB_ESCR1 0x000003ab |
| 403 | #define MSR_P4_MS_ESCR0 0x000003c0 |
| 404 | #define MSR_P4_MS_ESCR1 0x000003c1 |
| 405 | #define MSR_P4_PMH_ESCR0 0x000003ac |
| 406 | #define MSR_P4_PMH_ESCR1 0x000003ad |
| 407 | #define MSR_P4_RAT_ESCR0 0x000003bc |
| 408 | #define MSR_P4_RAT_ESCR1 0x000003bd |
| 409 | #define MSR_P4_SAAT_ESCR0 0x000003ae |
| 410 | #define MSR_P4_SAAT_ESCR1 0x000003af |
| 411 | #define MSR_P4_SSU_ESCR0 0x000003be |
| 412 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
| 413 | |
| 414 | #define MSR_P4_TBPU_ESCR0 0x000003c2 |
| 415 | #define MSR_P4_TBPU_ESCR1 0x000003c3 |
| 416 | #define MSR_P4_TC_ESCR0 0x000003c4 |
| 417 | #define MSR_P4_TC_ESCR1 0x000003c5 |
| 418 | #define MSR_P4_U2L_ESCR0 0x000003b0 |
| 419 | #define MSR_P4_U2L_ESCR1 0x000003b1 |
| 420 | |
| 421 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
| 422 | |
| 423 | /* Intel Core-based CPU performance counters */ |
| 424 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
| 425 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
| 426 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
| 427 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
| 428 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
| 429 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
| 430 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
| 431 | |
| 432 | /* Geode defined MSRs */ |
| 433 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
| 434 | |
| 435 | /* Intel VT MSRs */ |
| 436 | #define MSR_IA32_VMX_BASIC 0x00000480 |
| 437 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
| 438 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
| 439 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
| 440 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
| 441 | #define MSR_IA32_VMX_MISC 0x00000485 |
| 442 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
| 443 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
| 444 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
| 445 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
| 446 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
| 447 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
| 448 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
| 449 | |
| 450 | /* AMD-V MSRs */ |
| 451 | |
| 452 | #define MSR_VM_CR 0xc0010114 |
| 453 | #define MSR_VM_IGNNE 0xc0010115 |
| 454 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 455 | |
| 456 | #endif /* _ASM_X86_MSR_INDEX_H */ |