| Yoshihiro Shimoda | ad1a3a9 | 2007-12-03 22:58:45 +0900 | [diff] [blame] | 1 | /* |
| Nobuhiro Iwamatsu | a04ce4f | 2010-10-25 02:58:21 +0900 | [diff] [blame] | 2 | * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| Yoshihiro Shimoda | ad1a3a9 | 2007-12-03 22:58:45 +0900 | [diff] [blame] | 3 | * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Yoshihiro Shimoda | ad1a3a9 | 2007-12-03 22:58:45 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _ASM_CPU_SH3_H_ |
| 9 | #define _ASM_CPU_SH3_H_ |
| 10 | |
| 11 | /* cache control */ |
| 12 | #define CCR_CACHE_STOP 0x00000008 |
| 13 | #define CCR_CACHE_ENABLE 0x00000005 |
| 14 | #define CCR_CACHE_ICI 0x00000008 |
| 15 | |
| 16 | #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 |
| 17 | #define CACHE_OC_WAY_SHIFT 13 |
| 18 | #define CACHE_OC_NUM_ENTRIES 256 |
| 19 | #define CACHE_OC_ENTRY_SHIFT 4 |
| 20 | |
| Nobuhiro Iwamatsu | a04ce4f | 2010-10-25 02:58:21 +0900 | [diff] [blame] | 21 | #if defined(CONFIG_CPU_SH7706) |
| 22 | #include <asm/cpu_sh7706.h> |
| 23 | #elif defined(CONFIG_CPU_SH7710) |
| Nobuhiro Iwamatsu | fb3205b | 2008-01-15 23:25:25 +0900 | [diff] [blame] | 24 | #include <asm/cpu_sh7710.h> |
| 25 | #elif defined(CONFIG_CPU_SH7720) |
| Yoshihiro Shimoda | ad1a3a9 | 2007-12-03 22:58:45 +0900 | [diff] [blame] | 26 | #include <asm/cpu_sh7720.h> |
| 27 | #else |
| 28 | #error "Unknown SH3 variant" |
| 29 | #endif |
| 30 | |
| 31 | #endif /* _ASM_CPU_SH3_H_ */ |