| Wolfgang Denk | 6470255 | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2005-2006 Atmel Corporation |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Wolfgang Denk | 6470255 | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 5 | */ |
| Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 6 | #ifndef __AT32AP7000_HARDWARE_H__ |
| 7 | #define __AT32AP7000_HARDWARE_H__ |
| Wolfgang Denk | 6470255 | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 8 | |
| Haavard Skinnemoen | 23f62f1 | 2008-05-19 11:36:28 +0200 | [diff] [blame] | 9 | /* Internal and external memories */ |
| 10 | #define EBI_SRAM_CS0_BASE 0x00000000 |
| 11 | #define EBI_SRAM_CS0_SIZE 0x04000000 |
| 12 | #define EBI_SRAM_CS4_BASE 0x04000000 |
| 13 | #define EBI_SRAM_CS4_SIZE 0x04000000 |
| 14 | #define EBI_SRAM_CS2_BASE 0x08000000 |
| 15 | #define EBI_SRAM_CS2_SIZE 0x04000000 |
| 16 | #define EBI_SRAM_CS3_BASE 0x0c000000 |
| 17 | #define EBI_SRAM_CS3_SIZE 0x04000000 |
| 18 | #define EBI_SRAM_CS1_BASE 0x10000000 |
| 19 | #define EBI_SRAM_CS1_SIZE 0x10000000 |
| 20 | #define EBI_SRAM_CS5_BASE 0x20000000 |
| 21 | #define EBI_SRAM_CS5_SIZE 0x04000000 |
| 22 | |
| 23 | #define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE |
| 24 | #define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE |
| 25 | |
| 26 | #define INTERNAL_SRAM_BASE 0x24000000 |
| 27 | #define INTERNAL_SRAM_SIZE 0x00008000 |
| 28 | |
| Haavard Skinnemoen | 879cc87 | 2006-11-18 18:01:13 +0100 | [diff] [blame] | 29 | /* Devices on the High Speed Bus (HSB) */ |
| Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 30 | #define LCDC_BASE 0xFF000000 |
| 31 | #define DMAC_BASE 0xFF200000 |
| 32 | #define USB_FIFO 0xFF300000 |
| Haavard Skinnemoen | 879cc87 | 2006-11-18 18:01:13 +0100 | [diff] [blame] | 33 | |
| 34 | /* Devices on Peripheral Bus A (PBA) */ |
| Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 35 | #define ATMEL_BASE_SPI0 0xFFE00000 |
| 36 | #define ATMEL_BASE_SPI1 0xFFE00400 |
| 37 | #define ATMEL_BASE_TWI0 0xFFE00800 |
| 38 | #define ATMEL_BASE_USART0 0xFFE00C00 |
| 39 | #define ATMEL_BASE_USART1 0xFFE01000 |
| 40 | #define ATMEL_BASE_USART2 0xFFE01400 |
| 41 | #define ATMEL_BASE_USART3 0xFFE01800 |
| 42 | #define ATMEL_BASE_SSC0 0xFFE01C00 |
| 43 | #define ATMEL_BASE_SSC1 0xFFE02000 |
| 44 | #define ATMEL_BASE_SSC2 0xFFE02400 |
| 45 | #define ATMEL_BASE_PIOA 0xFFE02800 |
| 46 | #define ATMEL_BASE_PIOB 0xFFE02C00 |
| 47 | #define ATMEL_BASE_PIOC 0xFFE03000 |
| 48 | #define ATMEL_BASE_PIOD 0xFFE03400 |
| 49 | #define ATMEL_BASE_PIOE 0xFFE03800 |
| 50 | #define ATMEL_BASE_PSIF 0xFFE03C00 |
| Haavard Skinnemoen | 879cc87 | 2006-11-18 18:01:13 +0100 | [diff] [blame] | 51 | |
| 52 | /* Devices on Peripheral Bus B (PBB) */ |
| Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 53 | #define ATMEL_BASE_SM 0xFFF00000 |
| 54 | #define ATMEL_BASE_INTC 0xFFF00400 |
| 55 | #define ATMEL_BASE_HMATRIX 0xFFF00800 |
| 56 | #define ATMEL_BASE_TIMER0 0xFFF00C00 |
| 57 | #define ATMEL_BASE_TIMER1 0xFFF01000 |
| 58 | #define ATMEL_BASE_PWM 0xFFF01400 |
| 59 | #define ATMEL_BASE_MACB0 0xFFF01800 |
| 60 | #define ATMEL_BASE_MACB1 0xFFF01C00 |
| 61 | #define ATMEL_BASE_DAC 0xFFF02000 |
| 62 | #define ATMEL_BASE_MMCI 0xFFF02400 |
| 63 | #define ATMEL_BASE_AUDIOC 0xFFF02800 |
| 64 | #define ATMEL_BASE_HISI 0xFFF02C00 |
| 65 | #define ATMEL_BASE_USB 0xFFF03000 |
| 66 | #define ATMEL_BASE_HSMC 0xFFF03400 |
| 67 | #define ATMEL_BASE_HSDRAMC 0xFFF03800 |
| 68 | #define ATMEL_BASE_ECC 0xFFF03C00 |
| Wolfgang Denk | 6470255 | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 69 | |
| Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 70 | #endif /* __AT32AP7000_HARDWARE_H__ */ |