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git01.mediatek.com / filogic / uboot / d79de1d950d4779583a97be8eaab135d2bca3565 / . / arch / arm / include / asm / arch-mx25 / macro.h
blob: 6c41ea038a9b21b0d30c9c44c20f53e530c184d1 [file] [log] [blame]
Matthias Weisser82001ef2011-07-06 00:28:33 +0000[diff] [blame]1/*
2 * (C) Copyright 2011
3 * Matthias Weisser <weisserm@arcor.de>
4 *
5 * (C) Copyright 2009 DENX Software Engineering
6 * Author: John Rigby <jrigby@gmail.com>
7 *
8 * Common asm macros for imx25
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame^]10 * SPDX-License-Identifier: GPL-2.0+
Matthias Weisser82001ef2011-07-06 00:28:33 +0000[diff] [blame]11 */
12
13#ifndef __ASM_ARM_ARCH_MACRO_H__
14#define __ASM_ARM_ARCH_MACRO_H__
15#ifdef __ASSEMBLY__
16
17#include <asm/arch/imx-regs.h>
Stefano Babic2a1f1ac2011-09-05 04:32:28 +0000[diff] [blame]18#include <generated/asm-offsets.h>
Benoît Thébaudeauf58c48e2012-08-20 09:00:57 +0000[diff] [blame]19#include <asm/macro.h>
Matthias Weisser82001ef2011-07-06 00:28:33 +0000[diff] [blame]20
Benoît Thébaudeauf58c48e2012-08-20 09:00:57 +0000[diff] [blame]21/*
22 * AIPS setup - Only setup MPROTx registers.
23 * The PACR default values are good.
24 *
25 * Default argument values:
26 * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
27 * user-mode.
28 */
29.macro init_aips mpr=0x77777777
30 ldr r0, =IMX_AIPS1_BASE
31 ldr r1, =\mpr
32 str r1, [r0, #AIPS_MPR_0_7]
33 str r1, [r0, #AIPS_MPR_8_15]
34 ldr r2, =IMX_AIPS2_BASE
35 str r1, [r2, #AIPS_MPR_0_7]
36 str r1, [r2, #AIPS_MPR_8_15]
Matthias Weisser82001ef2011-07-06 00:28:33 +0000[diff] [blame]37.endm
38
Benoît Thébaudeauf58c48e2012-08-20 09:00:57 +0000[diff] [blame]39/*
40 * MAX (Multi-Layer AHB Crossbar Switch) setup
41 *
42 * Default argument values:
43 * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
44 * - SGPCR: always park on last master
45 * - MGPCR: restore default values
46 */
47.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
48 ldr r0, =IMX_MAX_BASE
49 ldr r1, =\mpr
50 str r1, [r0, #MAX_MPR0] /* for S0 */
51 str r1, [r0, #MAX_MPR1] /* for S1 */
52 str r1, [r0, #MAX_MPR2] /* for S2 */
53 str r1, [r0, #MAX_MPR3] /* for S3 */
54 str r1, [r0, #MAX_MPR4] /* for S4 */
55 ldr r1, =\sgpcr
56 str r1, [r0, #MAX_SGPCR0] /* for S0 */
57 str r1, [r0, #MAX_SGPCR1] /* for S1 */
58 str r1, [r0, #MAX_SGPCR2] /* for S2 */
59 str r1, [r0, #MAX_SGPCR3] /* for S3 */
60 str r1, [r0, #MAX_SGPCR4] /* for S4 */
61 ldr r1, =\mgpcr
62 str r1, [r0, #MAX_MGPCR0] /* for M0 */
63 str r1, [r0, #MAX_MGPCR1] /* for M1 */
64 str r1, [r0, #MAX_MGPCR2] /* for M2 */
65 str r1, [r0, #MAX_MGPCR3] /* for M3 */
66 str r1, [r0, #MAX_MGPCR4] /* for M4 */
67.endm
Matthias Weisser82001ef2011-07-06 00:28:33 +0000[diff] [blame]68
Benoît Thébaudeauf58c48e2012-08-20 09:00:57 +0000[diff] [blame]69/*
70 * M3IF setup
71 *
72 * Default argument values:
73 * - CTL:
74 * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
75 * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
76 * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
77 * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
78 * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
79 * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
80 * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
81 * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
82 * ------------
83 * 0x00000001
84 */
85.macro init_m3if ctl=0x00000001
86 /* M3IF Control Register (M3IFCTL) */
87 write32 IMX_M3IF_CTRL_BASE, \ctl
Matthias Weisser82001ef2011-07-06 00:28:33 +0000[diff] [blame]88.endm
89
90#endif /* __ASSEMBLY__ */
91#endif /* __ASM_ARM_ARCH_MACRO_H__ */