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Stefan Roesef2303272005-11-15 10:35:59 +01001/*
Matthias Fuchsc8452fa2007-07-09 10:10:06 +02002 * (C) Copyright 2005-2007
Stefan Roesef2303272005-11-15 10:35:59 +01003 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
Matthias Fuchsc8452fa2007-07-09 10:10:06 +020026#include <asm/io.h>
Stefan Roesef2303272005-11-15 10:35:59 +010027#include <command.h>
28#include <malloc.h>
29
Wolfgang Denk6405a152006-03-31 18:32:53 +020030DECLARE_GLOBAL_DATA_PTR;
Stefan Roesef2303272005-11-15 10:35:59 +010031
32extern void lxt971_no_sleep(void);
33
Stefan Roesef2303272005-11-15 10:35:59 +010034int board_early_init_f (void)
35{
36 /*
37 * IRQ 0-15 405GP internally generated; active high; level sensitive
38 * IRQ 16 405GP internally generated; active low; level sensitive
39 * IRQ 17-24 RESERVED
40 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
41 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
42 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
43 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
44 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
45 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
46 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
47 */
Stefan Roese707fd362009-09-24 09:55:50 +020048 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
50 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
51 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
52 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
53 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
54 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
Stefan Roesef2303272005-11-15 10:35:59 +010055
56 /*
57 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
58 */
Stefan Roese918010a2009-09-09 16:25:29 +020059 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
Stefan Roesef2303272005-11-15 10:35:59 +010060
61 /*
62 * Reset CPLD via GPIO12 (CS3) pin
63 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
Stefan Roesef2303272005-11-15 10:35:59 +010065 udelay(1000); /* wait 1ms */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
Stefan Roesef2303272005-11-15 10:35:59 +010067 udelay(1000); /* wait 1ms */
68
69 return 0;
70}
71
Stefan Roesef2303272005-11-15 10:35:59 +010072int misc_init_r (void)
73{
Stefan Roesef2303272005-11-15 10:35:59 +010074 /* adjust flash start and offset */
75 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
76 gd->bd->bi_flashoffset = 0;
77
Wolfgang Denka1be4762008-05-20 16:00:29 +020078 /*
Stefan Roesef2303272005-11-15 10:35:59 +010079 * Setup and enable EEPROM write protection
80 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
Stefan Roesef2303272005-11-15 10:35:59 +010082
83 return (0);
84}
85
86
87/*
88 * Check Board Identity:
89 */
Matthias Fuchsfaac7432009-02-20 10:19:18 +010090#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
Stefan Roesef2303272005-11-15 10:35:59 +010091int checkboard (void)
92{
Stefan Roese1586ded2006-01-18 20:06:44 +010093 char str[64];
Stefan Roesef2303272005-11-15 10:35:59 +010094 int flashcnt;
95 int delay;
Stefan Roesef2303272005-11-15 10:35:59 +010096
97 puts ("Board: ");
98
Wolfgang Denk76af2782010-07-24 21:55:43 +020099 if (getenv_f("serial#", str, sizeof(str)) == -1) {
Stefan Roesef2303272005-11-15 10:35:59 +0100100 puts ("### No HW ID - assuming CMS700");
101 } else {
102 puts(str);
103 }
104
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100105 printf(" (PLD-Version=%02d)\n",
106 in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
Stefan Roesef2303272005-11-15 10:35:59 +0100107
108 /*
109 * Flash LEDs
110 */
111 for (flashcnt = 0; flashcnt < 3; flashcnt++) {
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100112 out_8((void *)LED_REG, 0x00); /* LEDs off */
Stefan Roesef2303272005-11-15 10:35:59 +0100113 for (delay = 0; delay < 100; delay++)
114 udelay(1000);
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100115 out_8((void *)LED_REG, 0x0f); /* LEDs on */
Stefan Roesef2303272005-11-15 10:35:59 +0100116 for (delay = 0; delay < 50; delay++)
117 udelay(1000);
118 }
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100119 out_8((void *)LED_REG, 0x70);
Stefan Roesef2303272005-11-15 10:35:59 +0100120
121 return 0;
122}
123
124/* ------------------------------------------------------------------------- */
125
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#if defined(CONFIG_SYS_EEPROM_WREN)
Stefan Roesef2303272005-11-15 10:35:59 +0100127/* Input: <dev_addr> I2C address of EEPROM device to enable.
128 * <state> -1: deliver current state
129 * 0: disable write
130 * 1: enable write
131 * Returns: -1: wrong device address
132 * 0: dis-/en- able done
133 * 0/1: current state if <state> was -1.
134 */
135int eeprom_write_enable (unsigned dev_addr, int state)
136{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
Stefan Roesef2303272005-11-15 10:35:59 +0100138 return -1;
139 } else {
140 switch (state) {
141 case 1:
142 /* Enable write access, clear bit GPIO_SINT2. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
Stefan Roesef2303272005-11-15 10:35:59 +0100144 state = 0;
145 break;
146 case 0:
147 /* Disable write access, set bit GPIO_SINT2. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
Stefan Roesef2303272005-11-15 10:35:59 +0100149 state = 0;
150 break;
151 default:
152 /* Read current status back. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153 state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
Stefan Roesef2303272005-11-15 10:35:59 +0100154 break;
155 }
156 }
157 return state;
158}
159
Wolfgang Denk6262d0212010-06-28 22:00:46 +0200160int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Stefan Roesef2303272005-11-15 10:35:59 +0100161{
162 int query = argc == 1;
163 int state = 0;
164
165 if (query) {
166 /* Query write access state. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
Stefan Roesef2303272005-11-15 10:35:59 +0100168 if (state < 0) {
169 puts ("Query of write access state failed.\n");
170 } else {
171 printf ("Write access for device 0x%0x is %sabled.\n",
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
Stefan Roesef2303272005-11-15 10:35:59 +0100173 state = 0;
174 }
175 } else {
176 if ('0' == argv[1][0]) {
177 /* Disable write access. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
Stefan Roesef2303272005-11-15 10:35:59 +0100179 } else {
180 /* Enable write access. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
Stefan Roesef2303272005-11-15 10:35:59 +0100182 }
183 if (state < 0) {
184 puts ("Setup of write access state failed.\n");
185 }
186 }
187
188 return state;
189}
190
191U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200192 "Enable / disable / query EEPROM write access",
193 ""
194);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
Stefan Roesef2303272005-11-15 10:35:59 +0100196
197/* ------------------------------------------------------------------------- */
198
Stefan Roesef2303272005-11-15 10:35:59 +0100199void reset_phy(void)
200{
201#ifdef CONFIG_LXT971_NO_SLEEP
202
203 /*
204 * Disable sleep mode in LXT971
205 */
206 lxt971_no_sleep();
207#endif
208}