| wdenk | 0442ed8 | 2002-11-03 10:24:00 +0000 | [diff] [blame] | 1 | /*----------------------------------------------------------------------------+ |
| 2 | | |
| 3 | | This source code has been made available to you by IBM on an AS-IS |
| 4 | | basis. Anyone receiving this source is licensed under IBM |
| 5 | | copyrights to use it in any way he or she deems fit, including |
| 6 | | copying it, modifying it, compiling it, and redistributing it either |
| 7 | | with or without modifications. No license under IBM patents or |
| 8 | | patent applications is to be implied by the copyright license. |
| 9 | | |
| 10 | | Any user of this software should understand that IBM cannot provide |
| 11 | | technical support for this software and will not be responsible for |
| 12 | | any consequences resulting from the use of this software. |
| 13 | | |
| 14 | | Any person who transfers this source code or any derivative work |
| 15 | | must include the IBM copyright notice, this paragraph, and the |
| 16 | | preceding two paragraphs in the transferred software. |
| 17 | | |
| 18 | | COPYRIGHT I B M CORPORATION 1999 |
| 19 | | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
| 20 | +----------------------------------------------------------------------------*/ |
| 21 | |
| 22 | #ifndef __PPC405_H__ |
| 23 | #define __PPC405_H__ |
| 24 | |
| 25 | /*--------------------------------------------------------------------- */ |
| 26 | /* Special Purpose Registers */ |
| 27 | /*--------------------------------------------------------------------- */ |
| 28 | #define srr2 0x3de /* save/restore register 2 */ |
| 29 | #define srr3 0x3df /* save/restore register 3 */ |
| 30 | #define dbsr 0x3f0 /* debug status register */ |
| 31 | #define dbcr0 0x3f2 /* debug control register 0 */ |
| 32 | #define dbcr1 0x3bd /* debug control register 1 */ |
| 33 | #define iac1 0x3f4 /* instruction address comparator 1 */ |
| 34 | #define iac2 0x3f5 /* instruction address comparator 2 */ |
| 35 | #define iac3 0x3b4 /* instruction address comparator 3 */ |
| 36 | #define iac4 0x3b5 /* instruction address comparator 4 */ |
| 37 | #define dac1 0x3f6 /* data address comparator 1 */ |
| 38 | #define dac2 0x3f7 /* data address comparator 2 */ |
| 39 | #define dccr 0x3fa /* data cache control register */ |
| 40 | #define iccr 0x3fb /* instruction cache control register */ |
| 41 | #define esr 0x3d4 /* execption syndrome register */ |
| 42 | #define dear 0x3d5 /* data exeption address register */ |
| 43 | #define evpr 0x3d6 /* exeption vector prefix register */ |
| 44 | #define tsr 0x3d8 /* timer status register */ |
| 45 | #define tcr 0x3da /* timer control register */ |
| 46 | #define pit 0x3db /* programmable interval timer */ |
| 47 | #define sgr 0x3b9 /* storage guarded reg */ |
| 48 | #define dcwr 0x3ba /* data cache write-thru reg*/ |
| 49 | #define sler 0x3bb /* storage little-endian reg */ |
| 50 | #define cdbcr 0x3d7 /* cache debug cntrl reg */ |
| 51 | #define icdbdr 0x3d3 /* instr cache dbug data reg*/ |
| 52 | #define ccr0 0x3b3 /* core configuration register */ |
| 53 | #define dvc1 0x3b6 /* data value compare register 1 */ |
| 54 | #define dvc2 0x3b7 /* data value compare register 2 */ |
| 55 | #define pid 0x3b1 /* process ID */ |
| 56 | #define su0r 0x3bc /* storage user-defined register 0 */ |
| 57 | #define zpr 0x3b0 /* zone protection regsiter */ |
| 58 | |
| 59 | #define tbl 0x11c /* time base lower - privileged write */ |
| 60 | #define tbu 0x11d /* time base upper - privileged write */ |
| 61 | |
| 62 | #define sprg4r 0x104 /* Special purpose general 4 - read only */ |
| 63 | #define sprg5r 0x105 /* Special purpose general 5 - read only */ |
| 64 | #define sprg6r 0x106 /* Special purpose general 6 - read only */ |
| 65 | #define sprg7r 0x107 /* Special purpose general 7 - read only */ |
| 66 | #define sprg4w 0x114 /* Special purpose general 4 - write only */ |
| 67 | #define sprg5w 0x115 /* Special purpose general 5 - write only */ |
| 68 | #define sprg6w 0x116 /* Special purpose general 6 - write only */ |
| 69 | #define sprg7w 0x117 /* Special purpose general 7 - write only */ |
| 70 | |
| 71 | /****************************************************************************** |
| 72 | * Special for PPC405GP |
| 73 | ******************************************************************************/ |
| 74 | |
| 75 | /****************************************************************************** |
| 76 | * DMA |
| 77 | ******************************************************************************/ |
| 78 | #define DMA_DCR_BASE 0x100 |
| 79 | #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ |
| 80 | #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ |
| 81 | #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ |
| 82 | #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ |
| 83 | #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ |
| 84 | #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ |
| 85 | #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ |
| 86 | #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ |
| 87 | #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ |
| 88 | #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ |
| 89 | #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ |
| 90 | #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ |
| 91 | #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ |
| 92 | #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ |
| 93 | #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ |
| 94 | #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ |
| 95 | #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ |
| 96 | #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ |
| 97 | #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ |
| 98 | #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ |
| 99 | #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ |
| 100 | #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ |
| 101 | #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ |
| 102 | |
| 103 | /****************************************************************************** |
| 104 | * Universal interrupt controller |
| 105 | ******************************************************************************/ |
| 106 | #define UIC_DCR_BASE 0xc0 |
| 107 | #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ |
| 108 | #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ |
| 109 | #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ |
| 110 | #define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ |
| 111 | #define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ |
| 112 | #define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ |
| 113 | #define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ |
| 114 | #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ |
| 115 | #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ |
| 116 | |
| 117 | /*-----------------------------------------------------------------------------+ |
| 118 | | Universal interrupt controller interrupts |
| 119 | +-----------------------------------------------------------------------------*/ |
| 120 | #define UIC_UART0 0x80000000 /* UART 0 */ |
| 121 | #define UIC_UART1 0x40000000 /* UART 1 */ |
| 122 | #define UIC_IIC 0x20000000 /* IIC */ |
| 123 | #define UIC_EXT_MAST 0x10000000 /* External Master */ |
| 124 | #define UIC_PCI 0x08000000 /* PCI write to command reg */ |
| 125 | #define UIC_DMA0 0x04000000 /* DMA chan. 0 */ |
| 126 | #define UIC_DMA1 0x02000000 /* DMA chan. 1 */ |
| 127 | #define UIC_DMA2 0x01000000 /* DMA chan. 2 */ |
| 128 | #define UIC_DMA3 0x00800000 /* DMA chan. 3 */ |
| 129 | #define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ |
| 130 | #define UIC_MAL_SERR 0x00200000 /* MAL SERR */ |
| 131 | #define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ |
| 132 | #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ |
| 133 | #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ |
| 134 | #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ |
| 135 | #define UIC_ENET 0x00010000 /* Ethernet */ |
| 136 | #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ |
| 137 | #define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */ |
| 138 | #define UIC_PCI_PM 0x00002000 /* PCI Power Management */ |
| 139 | #define UIC_EXT0 0x00000040 /* External interrupt 0 */ |
| 140 | #define UIC_EXT1 0x00000020 /* External interrupt 1 */ |
| 141 | #define UIC_EXT2 0x00000010 /* External interrupt 2 */ |
| 142 | #define UIC_EXT3 0x00000008 /* External interrupt 3 */ |
| 143 | #define UIC_EXT4 0x00000004 /* External interrupt 4 */ |
| 144 | #define UIC_EXT5 0x00000002 /* External interrupt 5 */ |
| 145 | #define UIC_EXT6 0x00000001 /* External interrupt 6 */ |
| 146 | |
| 147 | /****************************************************************************** |
| 148 | * SDRAM Controller |
| 149 | ******************************************************************************/ |
| 150 | #define SDRAM_DCR_BASE 0x10 |
| 151 | #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ |
| 152 | #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ |
| 153 | /* values for memcfga register - indirect addressing of these regs */ |
| 154 | #define mem_besra 0x00 /* bus error syndrome reg a */ |
| 155 | #define mem_besrsa 0x04 /* bus error syndrome reg set a */ |
| 156 | #define mem_besrb 0x08 /* bus error syndrome reg b */ |
| 157 | #define mem_besrsb 0x0c /* bus error syndrome reg set b */ |
| 158 | #define mem_bear 0x10 /* bus error address reg */ |
| 159 | #define mem_mcopt1 0x20 /* memory controller options 1 */ |
| 160 | #define mem_rtr 0x30 /* refresh timer reg */ |
| 161 | #define mem_pmit 0x34 /* power management idle timer */ |
| 162 | #define mem_mb0cf 0x40 /* memory bank 0 configuration */ |
| 163 | #define mem_mb1cf 0x44 /* memory bank 1 configuration */ |
| 164 | #define mem_mb2cf 0x48 /* memory bank 2 configuration */ |
| 165 | #define mem_mb3cf 0x4c /* memory bank 3 configuration */ |
| 166 | #define mem_sdtr1 0x80 /* timing reg 1 */ |
| 167 | #define mem_ecccf 0x94 /* ECC configuration */ |
| 168 | #define mem_eccerr 0x98 /* ECC error status */ |
| 169 | |
| 170 | /****************************************************************************** |
| 171 | * Decompression Controller |
| 172 | ******************************************************************************/ |
| 173 | #define DECOMP_DCR_BASE 0x14 |
| 174 | #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ |
| 175 | #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ |
| 176 | /* values for kiar register - indirect addressing of these regs */ |
| 177 | #define kitor0 0x00 /* index table origin register 0 */ |
| 178 | #define kitor1 0x01 /* index table origin register 1 */ |
| 179 | #define kitor2 0x02 /* index table origin register 2 */ |
| 180 | #define kitor3 0x03 /* index table origin register 3 */ |
| 181 | #define kaddr0 0x04 /* address decode definition regsiter 0 */ |
| 182 | #define kaddr1 0x05 /* address decode definition regsiter 1 */ |
| 183 | #define kconf 0x40 /* decompression core config register */ |
| 184 | #define kid 0x41 /* decompression core ID register */ |
| 185 | #define kver 0x42 /* decompression core version # reg */ |
| 186 | #define kpear 0x50 /* bus error addr reg (PLB addr) */ |
| 187 | #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ |
| 188 | #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ |
| 189 | #define kesr0s 0x53 /* bus error status reg 0 (set) */ |
| 190 | /* There are 0x400 of the following registers, from krom0 to krom3ff*/ |
| 191 | /* Only the first one is given here. */ |
| 192 | #define krom0 0x400 /* SRAM/ROM read/write */ |
| 193 | |
| 194 | /****************************************************************************** |
| 195 | * Power Management |
| 196 | ******************************************************************************/ |
| 197 | #define POWERMAN_DCR_BASE 0xb8 |
| 198 | #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ |
| 199 | #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ |
| 200 | #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ |
| 201 | |
| 202 | /****************************************************************************** |
| 203 | * Extrnal Bus Controller |
| 204 | ******************************************************************************/ |
| 205 | #define EBC_DCR_BASE 0x12 |
| 206 | #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ |
| 207 | #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ |
| 208 | /* values for ebccfga register - indirect addressing of these regs */ |
| 209 | #define pb0cr 0x00 /* periph bank 0 config reg */ |
| 210 | #define pb1cr 0x01 /* periph bank 1 config reg */ |
| 211 | #define pb2cr 0x02 /* periph bank 2 config reg */ |
| 212 | #define pb3cr 0x03 /* periph bank 3 config reg */ |
| 213 | #define pb4cr 0x04 /* periph bank 4 config reg */ |
| 214 | #define pb5cr 0x05 /* periph bank 5 config reg */ |
| 215 | #define pb6cr 0x06 /* periph bank 6 config reg */ |
| 216 | #define pb7cr 0x07 /* periph bank 7 config reg */ |
| 217 | #define pb0ap 0x10 /* periph bank 0 access parameters */ |
| 218 | #define pb1ap 0x11 /* periph bank 1 access parameters */ |
| 219 | #define pb2ap 0x12 /* periph bank 2 access parameters */ |
| 220 | #define pb3ap 0x13 /* periph bank 3 access parameters */ |
| 221 | #define pb4ap 0x14 /* periph bank 4 access parameters */ |
| 222 | #define pb5ap 0x15 /* periph bank 5 access parameters */ |
| 223 | #define pb6ap 0x16 /* periph bank 6 access parameters */ |
| 224 | #define pb7ap 0x17 /* periph bank 7 access parameters */ |
| 225 | #define pbear 0x20 /* periph bus error addr reg */ |
| 226 | #define pbesr0 0x21 /* periph bus error status reg 0 */ |
| 227 | #define pbesr1 0x22 /* periph bus error status reg 1 */ |
| 228 | #define epcr 0x23 /* external periph control reg */ |
| 229 | |
| 230 | /****************************************************************************** |
| 231 | * Control |
| 232 | ******************************************************************************/ |
| 233 | #define CNTRL_DCR_BASE 0x0b0 |
| 234 | #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ |
| 235 | #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ |
| 236 | #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ |
| 237 | #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ |
| 238 | #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ |
| 239 | |
| 240 | /* Bit definitions */ |
| 241 | #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ |
| 242 | #define PLLMR_FWD_DIV_BYPASS 0xE0000000 |
| 243 | #define PLLMR_FWD_DIV_3 0xA0000000 |
| 244 | #define PLLMR_FWD_DIV_4 0x80000000 |
| 245 | #define PLLMR_FWD_DIV_6 0x40000000 |
| 246 | |
| 247 | #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ |
| 248 | #define PLLMR_FB_DIV_1 0x02000000 |
| 249 | #define PLLMR_FB_DIV_2 0x04000000 |
| 250 | #define PLLMR_FB_DIV_3 0x06000000 |
| 251 | #define PLLMR_FB_DIV_4 0x08000000 |
| 252 | |
| 253 | #define PLLMR_TUNING_MASK 0x01F80000 |
| 254 | |
| 255 | #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ |
| 256 | #define PLLMR_CPU_PLB_DIV_1 0x00000000 |
| 257 | #define PLLMR_CPU_PLB_DIV_2 0x00020000 |
| 258 | #define PLLMR_CPU_PLB_DIV_3 0x00040000 |
| 259 | #define PLLMR_CPU_PLB_DIV_4 0x00060000 |
| 260 | |
| 261 | #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ |
| 262 | #define PLLMR_OPB_PLB_DIV_1 0x00000000 |
| 263 | #define PLLMR_OPB_PLB_DIV_2 0x00008000 |
| 264 | #define PLLMR_OPB_PLB_DIV_3 0x00010000 |
| 265 | #define PLLMR_OPB_PLB_DIV_4 0x00018000 |
| 266 | |
| 267 | #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ |
| 268 | #define PLLMR_PCI_PLB_DIV_1 0x00000000 |
| 269 | #define PLLMR_PCI_PLB_DIV_2 0x00002000 |
| 270 | #define PLLMR_PCI_PLB_DIV_3 0x00004000 |
| 271 | #define PLLMR_PCI_PLB_DIV_4 0x00006000 |
| 272 | |
| 273 | #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ |
| 274 | #define PLLMR_EXB_PLB_DIV_2 0x00000000 |
| 275 | #define PLLMR_EXB_PLB_DIV_3 0x00000800 |
| 276 | #define PLLMR_EXB_PLB_DIV_4 0x00001000 |
| 277 | #define PLLMR_EXB_PLB_DIV_5 0x00001800 |
| 278 | |
| 279 | /* definitions for PPC405GPr (new mode strapping) */ |
| 280 | #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ |
| 281 | |
| 282 | #define PSR_PLL_FWD_MASK 0xC0000000 |
| 283 | #define PSR_PLL_FDBACK_MASK 0x30000000 |
| 284 | #define PSR_PLL_TUNING_MASK 0x0E000000 |
| 285 | #define PSR_PLB_CPU_MASK 0x01800000 |
| 286 | #define PSR_OPB_PLB_MASK 0x00600000 |
| 287 | #define PSR_PCI_PLB_MASK 0x00180000 |
| 288 | #define PSR_EB_PLB_MASK 0x00060000 |
| 289 | #define PSR_ROM_WIDTH_MASK 0x00018000 |
| 290 | #define PSR_ROM_LOC 0x00004000 |
| 291 | #define PSR_PCI_ASYNC_EN 0x00001000 |
| 292 | #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ |
| 293 | #define PSR_PCI_ARBIT_EN 0x00000400 |
| 294 | #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ |
| 295 | |
| 296 | /* |
| 297 | * PLL Voltage Controlled Oscillator (VCO) definitions |
| 298 | * Maximum and minimum values (in MHz) for correct PLL operation. |
| 299 | */ |
| 300 | #define VCO_MIN 400 |
| 301 | #define VCO_MAX 800 |
| 302 | |
| 303 | /****************************************************************************** |
| 304 | * Memory Access Layer |
| 305 | ******************************************************************************/ |
| 306 | #define MAL_DCR_BASE 0x180 |
| 307 | #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ |
| 308 | #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ |
| 309 | #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ |
| 310 | #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ |
| 311 | #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ |
| 312 | #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ |
| 313 | #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ |
| 314 | #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ |
| 315 | #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ |
| 316 | #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ |
| 317 | #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ |
| 318 | #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ |
| 319 | #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ |
| 320 | #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ |
| 321 | #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ |
| 322 | #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ |
| 323 | |
| 324 | /*----------------------------------------------------------------------------- |
| 325 | | IIC Register Offsets |
| 326 | '----------------------------------------------------------------------------*/ |
| 327 | #define IICMDBUF 0x00 |
| 328 | #define IICSDBUF 0x02 |
| 329 | #define IICLMADR 0x04 |
| 330 | #define IICHMADR 0x05 |
| 331 | #define IICCNTL 0x06 |
| 332 | #define IICMDCNTL 0x07 |
| 333 | #define IICSTS 0x08 |
| 334 | #define IICEXTSTS 0x09 |
| 335 | #define IICLSADR 0x0A |
| 336 | #define IICHSADR 0x0B |
| 337 | #define IICCLKDIV 0x0C |
| 338 | #define IICINTRMSK 0x0D |
| 339 | #define IICXFRCNT 0x0E |
| 340 | #define IICXTCNTLSS 0x0F |
| 341 | #define IICDIRECTCNTL 0x10 |
| 342 | |
| 343 | /*----------------------------------------------------------------------------- |
| 344 | | UART Register Offsets |
| 345 | '----------------------------------------------------------------------------*/ |
| 346 | #define DATA_REG 0x00 |
| 347 | #define DL_LSB 0x00 |
| 348 | #define DL_MSB 0x01 |
| 349 | #define INT_ENABLE 0x01 |
| 350 | #define FIFO_CONTROL 0x02 |
| 351 | #define LINE_CONTROL 0x03 |
| 352 | #define MODEM_CONTROL 0x04 |
| 353 | #define LINE_STATUS 0x05 |
| 354 | #define MODEM_STATUS 0x06 |
| 355 | #define SCRATCH 0x07 |
| 356 | |
| 357 | /****************************************************************************** |
| 358 | * On Chip Memory |
| 359 | ******************************************************************************/ |
| 360 | #define OCM_DCR_BASE 0x018 |
| 361 | #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ |
| 362 | #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ |
| 363 | #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ |
| 364 | #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ |
| 365 | |
| 366 | |
| 367 | /* |
| 368 | * Macro for accessing the indirect EBC register |
| 369 | */ |
| 370 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) |
| 371 | #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) |
| 372 | |
| 373 | |
| 374 | #ifndef __ASSEMBLY__ |
| 375 | |
| 376 | typedef struct |
| 377 | { |
| 378 | unsigned long pllFwdDiv; |
| 379 | unsigned long pllFwdDivB; |
| 380 | unsigned long pllFbkDiv; |
| 381 | unsigned long pllPlbDiv; |
| 382 | unsigned long pllPciDiv; |
| 383 | unsigned long pllExtBusDiv; |
| 384 | unsigned long pllOpbDiv; |
| 385 | unsigned long freqVCOMhz; /* in MHz */ |
| 386 | unsigned long freqProcessor; |
| 387 | unsigned long freqPLB; |
| 388 | unsigned long freqPCI; |
| 389 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ |
| 390 | unsigned long pciClkSync; /* PCI clock is synchronous */ |
| 391 | } PPC405_SYS_INFO; |
| 392 | |
| 393 | #endif /* _ASMLANGUAGE */ |
| 394 | |
| 395 | #define RESET_VECTOR 0xfffffffc |
| 396 | #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache |
| 397 | line aligned data. */ |
| 398 | |
| 399 | #endif /* __PPC405_H__ */ |
| 400 | |