Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for MPR2 |
| 4 | * |
| 5 | * Copyright (C) 2008 |
| 6 | * Mark Jonas <mark.jonas@de.bosch.com> |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __MPR2_H |
| 10 | #define __MPR2_H |
| 11 | |
| 12 | /* Supported commands */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 13 | |
| 14 | /* Default environment variables */ |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 15 | #define CONFIG_BOOTFILE "/boot/zImage" |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 16 | #define CONFIG_LOADADDR 0x8E000000 |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 17 | |
| 18 | /* CPU and platform */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 19 | #define CONFIG_CPU_SH7720 1 |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 20 | |
Vladimir Zapolskiy | 5e72b84 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 21 | #define CONFIG_DISPLAY_BOARDINFO |
| 22 | |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 23 | /* U-Boot internals */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 24 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ |
| 25 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
| 26 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 27 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
| 28 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 29 | |
| 30 | /* Memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 31 | #define CONFIG_SYS_SDRAM_BASE 0x8C000000 |
| 32 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
| 33 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 34 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 35 | |
| 36 | /* Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 37 | #define CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 38 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 40 | #define CONFIG_SYS_FLASH_BASE 0xA0000000 |
| 41 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 42 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 43 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 44 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 45 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 47 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
| 48 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 49 | |
| 50 | /* Clocks */ |
| 51 | #define CONFIG_SYS_CLK_FREQ 24000000 |
Nobuhiro Iwamatsu | e698449 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 52 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 53 | |
| 54 | /* UART */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 55 | #define CONFIG_CONS_SCIF0 1 |
| 56 | |
| 57 | #endif /* __MPR2_H */ |