Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9RLEK board. |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 13 | #include <asm/hardware.h> |
| 14 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 15 | /* ARM asynchronous clock */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 16 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 17 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 18 | |
Jean-Christophe PLAGNIOL-VILLARD | 23164f1 | 2009-04-16 21:30:44 +0200 | [diff] [blame] | 19 | #define CONFIG_ARCH_CPU_INIT |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 20 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 21 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 22 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 23 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 24 | #define CONFIG_INITRD_TAG 1 |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 25 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 26 | #define CONFIG_ATMEL_LEGACY |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 27 | |
| 28 | /* |
| 29 | * Hardware drivers |
| 30 | */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 31 | |
Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 32 | /* LCD */ |
Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 33 | #define LCD_BPP LCD_COLOR8 |
| 34 | #define CONFIG_LCD_LOGO 1 |
| 35 | #undef LCD_TEST_PATTERN |
| 36 | #define CONFIG_LCD_INFO 1 |
| 37 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 |
Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 38 | #define CONFIG_ATMEL_LCD 1 |
| 39 | #define CONFIG_ATMEL_LCD_RGB565 1 |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 40 | /* Let board_init_f handle the framebuffer allocation */ |
| 41 | #undef CONFIG_FB_ADDR |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 42 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 43 | /* SDRAM */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 44 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 45 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 46 | |
| 47 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | 3cbbeb1 | 2017-04-18 15:28:27 +0800 | [diff] [blame] | 48 | (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 49 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 50 | /* NAND flash */ |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 51 | #ifdef CONFIG_CMD_NAND |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 53 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_NAND_DBW_8 1 |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 55 | /* our ALE is AD21 */ |
| 56 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 57 | /* our CLE is AD22 */ |
| 58 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 59 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 |
| 60 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 |
Wolfgang Denk | 1f79774 | 2009-07-18 21:52:24 +0200 | [diff] [blame] | 61 | |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 62 | #endif |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 63 | |
| 64 | /* Ethernet - not present */ |
| 65 | |
| 66 | /* USB - not supported */ |
| 67 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 69 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 70 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 72 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | #ifdef CONFIG_SYS_USE_DATAFLASH |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 74 | |
| 75 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
Wenyou.Yang@microchip.com | 5d7fd3e | 2017-07-21 13:40:10 +0800 | [diff] [blame] | 76 | #define CONFIG_ENV_OFFSET 0x4200 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 77 | #define CONFIG_ENV_SIZE 0x4200 |
Wenyou.Yang@microchip.com | 5d7fd3e | 2017-07-21 13:40:10 +0800 | [diff] [blame] | 78 | #define CONFIG_ENV_SECT_SIZE 0x210 |
| 79 | #define CONFIG_ENV_SPI_MAX_HZ 15000000 |
| 80 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 81 | "sf read 0x22000000 0x84000 0x294000; " \ |
| 82 | "bootm 0x22000000" |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 83 | |
Wu, Josh | 7ff194f | 2015-02-02 17:51:01 +0800 | [diff] [blame] | 84 | #elif CONFIG_SYS_USE_NANDFLASH |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 85 | |
| 86 | /* bootstrap + u-boot + env + linux in nandflash */ |
Nicolas Ferre | 6492244 | 2018-05-09 10:30:25 +0300 | [diff] [blame] | 87 | #define CONFIG_ENV_OFFSET 0x140000 |
Wu, Josh | f8e70d9 | 2015-02-03 11:38:30 +0800 | [diff] [blame] | 88 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 89 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
Wu, Josh | f8e70d9 | 2015-02-03 11:38:30 +0800 | [diff] [blame] | 90 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \ |
| 91 | "nand read 0x21000000 0x180000 0x80000; " \ |
| 92 | "bootz 0x22000000 - 0x21000000" |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 93 | |
Wu, Josh | 7ff194f | 2015-02-02 17:51:01 +0800 | [diff] [blame] | 94 | #else /* CONFIG_SYS_USE_MMC */ |
| 95 | |
| 96 | /* bootstrap + u-boot + env + linux in mmc */ |
Wu, Josh | 7ff194f | 2015-02-02 17:51:01 +0800 | [diff] [blame] | 97 | #define CONFIG_ENV_SIZE 0x4000 |
| 98 | #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \ |
| 99 | "fatload mmc 0:1 0x22000000 zImage; " \ |
| 100 | "bootz 0x22000000 - 0x21000000" |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 101 | #endif |
| 102 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 103 | /* |
| 104 | * Size of malloc() pool |
| 105 | */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 106 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 107 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 108 | #endif |