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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peter Korsgaard85ec2db2012-10-18 01:21:09 +00002/*
3 * board.c
4 *
5 * Board functions for TI AM335X based boards
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
Peter Korsgaard85ec2db2012-10-18 01:21:09 +00008 */
9
10#include <common.h>
Lokesh Vutla2fe7c792017-04-26 13:37:08 +053011#include <dm.h>
Simon Glass79fd2142019-08-01 09:46:43 -060012#include <env.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000013#include <errno.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060014#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070015#include <init.h>
Simon Glass9bc15642020-02-03 07:36:16 -070016#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <net.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000018#include <spl.h>
Lokesh Vutlaabb44e62016-05-16 11:47:29 +053019#include <serial.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000020#include <asm/arch/cpu.h>
21#include <asm/arch/hardware.h>
22#include <asm/arch/omap.h>
23#include <asm/arch/ddr_defs.h>
24#include <asm/arch/clock.h>
Lokesh Vutla0d144f52016-05-16 11:47:26 +053025#include <asm/arch/clk_synthesizer.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000026#include <asm/arch/gpio.h>
27#include <asm/arch/mmc_host_def.h>
28#include <asm/arch/sys_proto.h>
Steve Kipiszbe9b6f82013-07-18 15:13:03 -040029#include <asm/arch/mem.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000030#include <asm/io.h>
31#include <asm/emif.h>
32#include <asm/gpio.h>
Semen Protsenkoa8cb0222017-06-02 18:00:00 +030033#include <asm/omap_common.h>
Andrew F. Davisbd249152016-08-30 14:06:24 -050034#include <asm/omap_sec_common.h>
Lokesh Vutla2fe7c792017-04-26 13:37:08 +053035#include <asm/omap_mmc.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000036#include <i2c.h>
37#include <miiphy.h>
38#include <cpsw.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060039#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060040#include <linux/delay.h>
Tom Rini52437072013-08-30 16:28:46 -040041#include <power/tps65217.h>
42#include <power/tps65910.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060043#include <env_internal.h>
Tom Rini303bfe82013-10-01 12:32:04 -040044#include <watchdog.h>
Nishanth Menon2afa70d2016-02-24 12:30:55 -060045#include "../common/board_detect.h"
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000046#include "board.h"
47
48DECLARE_GLOBAL_DATA_PTR;
49
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000050/* GPIO that controls power to DDR on EVM-SK */
Lokesh Vutla0d144f52016-05-16 11:47:26 +053051#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
52#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
53#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
54#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
55#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
56#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
57#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
Roger Quadrosbcb4ee82016-08-24 15:35:50 +030058#define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
59#define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000060
61static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
62
Roger Quadrosbcb4ee82016-08-24 15:35:50 +030063#define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
64#define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
65
66#define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
67#define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
68
69#define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
70#define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
71
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000072/*
73 * Read header information from EEPROM into global structure.
74 */
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053075#ifdef CONFIG_TI_I2C_BOARD_DETECT
76void do_board_detect(void)
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000077{
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053078 enable_i2c0_pin_mux();
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +010079#ifndef CONFIG_DM_I2C
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053080 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +010081#endif
Simon Glass4df67572017-05-12 21:09:55 -060082 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
83 CONFIG_EEPROM_CHIP_ADDRESS))
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053084 printf("ti_i2c_eeprom_init failed\n");
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000085}
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053086#endif
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000087
Lokesh Vutlaabb44e62016-05-16 11:47:29 +053088#ifndef CONFIG_DM_SERIAL
89struct serial_device *default_serial_console(void)
90{
91 if (board_is_icev2())
92 return &eserial4_device;
93 else
94 return &eserial1_device;
95}
96#endif
97
Tom Rini8de09df2014-04-09 08:25:57 -040098#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +000099static const struct ddr_data ddr2_data = {
Tom Rini7f50a572014-07-07 21:40:16 -0400100 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
101 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
102 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000103};
104
105static const struct cmd_control ddr2_cmd_ctrl_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000106 .cmd0csratio = MT47H128M16RT25E_RATIO,
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000107
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000108 .cmd1csratio = MT47H128M16RT25E_RATIO,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000109
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000110 .cmd2csratio = MT47H128M16RT25E_RATIO,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000111};
112
113static const struct emif_regs ddr2_emif_reg_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000114 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
115 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
116 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
117 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
118 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
119 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000120};
121
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200122static const struct emif_regs ddr2_evm_emif_reg_data = {
123 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
124 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
125 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
126 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
127 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
128 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
129 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
130};
131
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000132static const struct ddr_data ddr3_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000133 .datardsratio0 = MT41J128MJT125_RD_DQS,
134 .datawdsratio0 = MT41J128MJT125_WR_DQS,
135 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
136 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000137};
138
Tom Rini385bc752013-03-21 04:30:02 +0000139static const struct ddr_data ddr3_beagleblack_data = {
140 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
141 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
142 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
143 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
Tom Rini385bc752013-03-21 04:30:02 +0000144};
145
Jeff Lance7c03a222013-01-14 05:32:20 +0000146static const struct ddr_data ddr3_evm_data = {
147 .datardsratio0 = MT41J512M8RH125_RD_DQS,
148 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
149 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
150 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
Jeff Lance7c03a222013-01-14 05:32:20 +0000151};
152
Lokesh Vutla5837b902016-05-16 11:47:24 +0530153static const struct ddr_data ddr3_icev2_data = {
154 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
155 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
156 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
157 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
158};
159
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000160static const struct cmd_control ddr3_cmd_ctrl_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000161 .cmd0csratio = MT41J128MJT125_RATIO,
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000162 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000163
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000164 .cmd1csratio = MT41J128MJT125_RATIO,
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000165 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000166
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000167 .cmd2csratio = MT41J128MJT125_RATIO,
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000168 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000169};
170
Tom Rini385bc752013-03-21 04:30:02 +0000171static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
172 .cmd0csratio = MT41K256M16HA125E_RATIO,
Tom Rini385bc752013-03-21 04:30:02 +0000173 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
174
175 .cmd1csratio = MT41K256M16HA125E_RATIO,
Tom Rini385bc752013-03-21 04:30:02 +0000176 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
177
178 .cmd2csratio = MT41K256M16HA125E_RATIO,
Tom Rini385bc752013-03-21 04:30:02 +0000179 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
180};
181
Jeff Lance7c03a222013-01-14 05:32:20 +0000182static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
183 .cmd0csratio = MT41J512M8RH125_RATIO,
Jeff Lance7c03a222013-01-14 05:32:20 +0000184 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
185
186 .cmd1csratio = MT41J512M8RH125_RATIO,
Jeff Lance7c03a222013-01-14 05:32:20 +0000187 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
188
189 .cmd2csratio = MT41J512M8RH125_RATIO,
Jeff Lance7c03a222013-01-14 05:32:20 +0000190 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
191};
192
Lokesh Vutla5837b902016-05-16 11:47:24 +0530193static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
194 .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
195 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
196
197 .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
198 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
199
200 .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
201 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
202};
203
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000204static struct emif_regs ddr3_emif_reg_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000205 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
206 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
207 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
208 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
209 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
210 .zq_config = MT41J128MJT125_ZQ_CFG,
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000211 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
212 PHY_EN_DYN_PWRDN,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000213};
Jeff Lance7c03a222013-01-14 05:32:20 +0000214
Tom Rini385bc752013-03-21 04:30:02 +0000215static struct emif_regs ddr3_beagleblack_emif_reg_data = {
216 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
217 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
218 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
219 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
220 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200221 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
Tom Rini385bc752013-03-21 04:30:02 +0000222 .zq_config = MT41K256M16HA125E_ZQ_CFG,
223 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
224};
225
Jeff Lance7c03a222013-01-14 05:32:20 +0000226static struct emif_regs ddr3_evm_emif_reg_data = {
227 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
228 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
229 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
230 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
231 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200232 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
Jeff Lance7c03a222013-01-14 05:32:20 +0000233 .zq_config = MT41J512M8RH125_ZQ_CFG,
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000234 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
235 PHY_EN_DYN_PWRDN,
Jeff Lance7c03a222013-01-14 05:32:20 +0000236};
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000237
Lokesh Vutla5837b902016-05-16 11:47:24 +0530238static struct emif_regs ddr3_icev2_emif_reg_data = {
239 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
240 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
241 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
242 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
243 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
244 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
245 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
246 PHY_EN_DYN_PWRDN,
247};
248
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000249#ifdef CONFIG_SPL_OS_BOOT
250int spl_start_uboot(void)
251{
Alex Kiernandf0df672018-04-19 04:32:53 +0000252#ifdef CONFIG_SPL_SERIAL_SUPPORT
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000253 /* break into full u-boot on 'c' */
Tom Rini810b5812014-03-28 12:03:38 -0400254 if (serial_tstc() && serial_getc() == 'c')
255 return 1;
Alex Kiernandf0df672018-04-19 04:32:53 +0000256#endif
Tom Rini810b5812014-03-28 12:03:38 -0400257
258#ifdef CONFIG_SPL_ENV_SUPPORT
259 env_init();
Simon Glass17539572017-08-03 12:22:07 -0600260 env_load();
Simon Glass22c34c22017-08-03 12:22:13 -0600261 if (env_get_yesno("boot_os") != 1)
Tom Rini810b5812014-03-28 12:03:38 -0400262 return 1;
263#endif
264
265 return 0;
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000266}
267#endif
268
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530269const struct dpll_params *get_dpll_ddr_params(void)
Tom Rini52437072013-08-30 16:28:46 -0400270{
Lokesh Vutla6302e532017-05-05 12:59:10 +0530271 int ind = get_sys_clk_index();
272
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530273 if (board_is_evm_sk())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530274 return &dpll_ddr3_303MHz[ind];
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500275 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530276 return &dpll_ddr3_400MHz[ind];
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530277 else if (board_is_evm_15_or_later())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530278 return &dpll_ddr3_303MHz[ind];
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530279 else
Lokesh Vutla6302e532017-05-05 12:59:10 +0530280 return &dpll_ddr2_266MHz[ind];
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530281}
Tom Rini52437072013-08-30 16:28:46 -0400282
Lokesh Vutla6302e532017-05-05 12:59:10 +0530283static u8 bone_not_connected_to_ac_power(void)
284{
285 if (board_is_bone()) {
286 uchar pmic_status_reg;
287 if (tps65217_reg_read(TPS65217_STATUS,
288 &pmic_status_reg))
289 return 1;
290 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
291 puts("No AC power, switching to default OPP\n");
292 return 1;
293 }
294 }
295 return 0;
296}
297
298const struct dpll_params *get_dpll_mpu_params(void)
299{
300 int ind = get_sys_clk_index();
301 int freq = am335x_get_efuse_mpu_max_freq(cdev);
302
303 if (bone_not_connected_to_ac_power())
304 freq = MPUPLL_M_600;
305
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500306 if (board_is_pb() || board_is_bone_lt())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530307 freq = MPUPLL_M_1000;
308
309 switch (freq) {
310 case MPUPLL_M_1000:
311 return &dpll_mpu_opp[ind][5];
312 case MPUPLL_M_800:
313 return &dpll_mpu_opp[ind][4];
314 case MPUPLL_M_720:
315 return &dpll_mpu_opp[ind][3];
316 case MPUPLL_M_600:
317 return &dpll_mpu_opp[ind][2];
318 case MPUPLL_M_500:
319 return &dpll_mpu_opp100;
320 case MPUPLL_M_300:
321 return &dpll_mpu_opp[ind][0];
322 }
323
324 return &dpll_mpu_opp[ind][0];
325}
326
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530327static void scale_vcores_bone(int freq)
328{
329 int usb_cur_lim, mpu_vdd;
Tom Rini52437072013-08-30 16:28:46 -0400330
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530331 /*
332 * Only perform PMIC configurations if board rev > A1
333 * on Beaglebone White
334 */
335 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
336 return;
Tom Rini52437072013-08-30 16:28:46 -0400337
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100338#ifndef CONFIG_DM_I2C
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530339 if (i2c_probe(TPS65217_CHIP_PM))
340 return;
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100341#else
342 if (power_tps65217_init(0))
343 return;
344#endif
345
Tom Rini52437072013-08-30 16:28:46 -0400346
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530347 /*
348 * On Beaglebone White we need to ensure we have AC power
349 * before increasing the frequency.
350 */
Lokesh Vutla6302e532017-05-05 12:59:10 +0530351 if (bone_not_connected_to_ac_power())
352 freq = MPUPLL_M_600;
Tom Rini52437072013-08-30 16:28:46 -0400353
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530354 /*
355 * Override what we have detected since we know if we have
356 * a Beaglebone Black it supports 1GHz.
357 */
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500358 if (board_is_pb() || board_is_bone_lt())
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530359 freq = MPUPLL_M_1000;
Tom Rini52437072013-08-30 16:28:46 -0400360
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530361 switch (freq) {
362 case MPUPLL_M_1000:
363 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
364 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
365 break;
366 case MPUPLL_M_800:
367 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530368 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530369 break;
370 case MPUPLL_M_720:
371 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530372 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530373 break;
374 case MPUPLL_M_600:
375 case MPUPLL_M_500:
376 case MPUPLL_M_300:
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530377 default:
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530378 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
379 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
380 break;
381 }
Steve Kipisz5adac352013-08-14 10:51:31 -0400382
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530383 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
384 TPS65217_POWER_PATH,
385 usb_cur_lim,
386 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
387 puts("tps65217_reg_write failure\n");
Tom Rini52437072013-08-30 16:28:46 -0400388
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530389 /* Set DCDC3 (CORE) voltage to 1.10V */
390 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
391 TPS65217_DCDC_VOLT_SEL_1100MV)) {
392 puts("tps65217_voltage_update failure\n");
393 return;
394 }
Tom Rini52437072013-08-30 16:28:46 -0400395
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530396 /* Set DCDC2 (MPU) voltage */
397 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
398 puts("tps65217_voltage_update failure\n");
399 return;
400 }
Tom Rini52437072013-08-30 16:28:46 -0400401
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530402 /*
403 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
404 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
405 */
406 if (board_is_bone()) {
Tom Rini52437072013-08-30 16:28:46 -0400407 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530408 TPS65217_DEFLS1,
Tom Rini52437072013-08-30 16:28:46 -0400409 TPS65217_LDO_VOLTAGE_OUT_3_3,
410 TPS65217_LDO_MASK))
411 puts("tps65217_reg_write failure\n");
412 } else {
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530413 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
414 TPS65217_DEFLS1,
415 TPS65217_LDO_VOLTAGE_OUT_1_8,
416 TPS65217_LDO_MASK))
417 puts("tps65217_reg_write failure\n");
418 }
Tom Rini52437072013-08-30 16:28:46 -0400419
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530420 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
421 TPS65217_DEFLS2,
422 TPS65217_LDO_VOLTAGE_OUT_3_3,
423 TPS65217_LDO_MASK))
424 puts("tps65217_reg_write failure\n");
425}
Tom Rini52437072013-08-30 16:28:46 -0400426
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530427void scale_vcores_generic(int freq)
428{
429 int sil_rev, mpu_vdd;
Tom Rini52437072013-08-30 16:28:46 -0400430
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530431 /*
432 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
433 * MPU frequencies we support we use a CORE voltage of
434 * 1.10V. For MPU voltage we need to switch based on
435 * the frequency we are running at.
436 */
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100437#ifndef CONFIG_DM_I2C
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530438 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
439 return;
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100440#else
441 if (power_tps65910_init(0))
442 return;
443#endif
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530444 /*
445 * Depending on MPU clock and PG we will need a different
446 * VDD to drive at that speed.
447 */
448 sil_rev = readl(&cdev->deviceid) >> 28;
449 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
Tom Rini52437072013-08-30 16:28:46 -0400450
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530451 /* Tell the TPS65910 to use i2c */
452 tps65910_set_i2c_control();
Steve Kipisz5adac352013-08-14 10:51:31 -0400453
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530454 /* First update MPU voltage. */
455 if (tps65910_voltage_update(MPU, mpu_vdd))
456 return;
Tom Rini52437072013-08-30 16:28:46 -0400457
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530458 /* Second, update the CORE voltage. */
459 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
460 return;
461
Tom Rini52437072013-08-30 16:28:46 -0400462}
463
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530464void gpi2c_init(void)
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530465{
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530466 /* When needed to be invoked prior to BSS initialization */
467 static bool first_time = true;
468
469 if (first_time) {
470 enable_i2c0_pin_mux();
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100471#ifndef CONFIG_DM_I2C
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530472 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
473 CONFIG_SYS_OMAP24_I2C_SLAVE);
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100474#endif
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530475 first_time = false;
476 }
477}
478
479void scale_vcores(void)
480{
481 int freq;
482
483 gpi2c_init();
484 freq = am335x_get_efuse_mpu_max_freq(cdev);
485
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530486 if (board_is_beaglebonex())
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530487 scale_vcores_bone(freq);
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530488 else
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530489 scale_vcores_generic(freq);
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530490}
491
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530492void set_uart_mux_conf(void)
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000493{
Tom Rini986d7552014-08-01 09:53:24 -0400494#if CONFIG_CONS_INDEX == 1
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000495 enable_uart0_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400496#elif CONFIG_CONS_INDEX == 2
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400497 enable_uart1_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400498#elif CONFIG_CONS_INDEX == 3
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400499 enable_uart2_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400500#elif CONFIG_CONS_INDEX == 4
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400501 enable_uart3_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400502#elif CONFIG_CONS_INDEX == 5
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400503 enable_uart4_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400504#elif CONFIG_CONS_INDEX == 6
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400505 enable_uart5_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400506#endif
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530507}
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000508
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530509void set_mux_conf_regs(void)
510{
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600511 enable_board_pin_mux();
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530512}
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000513
Lokesh Vutla303b2672013-12-10 15:02:21 +0530514const struct ctrl_ioregs ioregs_evmsk = {
515 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
516 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
517 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
518 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
519 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
520};
521
522const struct ctrl_ioregs ioregs_bonelt = {
523 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
524 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
525 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
526 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
527 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
528};
529
530const struct ctrl_ioregs ioregs_evm15 = {
531 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
532 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
533 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
534 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
535 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
536};
537
538const struct ctrl_ioregs ioregs = {
539 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
540 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
541 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
542 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
543 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
544};
545
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530546void sdram_init(void)
547{
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600548 if (board_is_evm_sk()) {
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000549 /*
550 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
551 * This is safe enough to do on older revs.
552 */
553 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
554 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
555 }
556
Lokesh Vutla5837b902016-05-16 11:47:24 +0530557 if (board_is_icev2()) {
558 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
559 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
560 }
561
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600562 if (board_is_evm_sk())
Lokesh Vutla303b2672013-12-10 15:02:21 +0530563 config_ddr(303, &ioregs_evmsk, &ddr3_data,
Matt Porter65991ec2013-03-15 10:07:03 +0000564 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500565 else if (board_is_pb() || board_is_bone_lt())
Lokesh Vutla303b2672013-12-10 15:02:21 +0530566 config_ddr(400, &ioregs_bonelt,
Tom Rini385bc752013-03-21 04:30:02 +0000567 &ddr3_beagleblack_data,
568 &ddr3_beagleblack_cmd_ctrl_data,
569 &ddr3_beagleblack_emif_reg_data, 0);
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600570 else if (board_is_evm_15_or_later())
Lokesh Vutla303b2672013-12-10 15:02:21 +0530571 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
Matt Porter65991ec2013-03-15 10:07:03 +0000572 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
Lokesh Vutla5837b902016-05-16 11:47:24 +0530573 else if (board_is_icev2())
574 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
575 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
576 0);
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200577 else if (board_is_gp_evm())
578 config_ddr(266, &ioregs, &ddr2_data,
579 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000580 else
Lokesh Vutla303b2672013-12-10 15:02:21 +0530581 config_ddr(266, &ioregs, &ddr2_data,
Matt Porter65991ec2013-03-15 10:07:03 +0000582 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000583}
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530584#endif
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000585
Alex Kiernan20bba2e2018-04-01 09:22:37 +0000586#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
587 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300588static void request_and_set_gpio(int gpio, char *name, int val)
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530589{
590 int ret;
591
592 ret = gpio_request(gpio, name);
593 if (ret < 0) {
594 printf("%s: Unable to request %s\n", __func__, name);
595 return;
596 }
597
598 ret = gpio_direction_output(gpio, 0);
599 if (ret < 0) {
600 printf("%s: Unable to set %s as output\n", __func__, name);
601 goto err_free_gpio;
602 }
603
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300604 gpio_set_value(gpio, val);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530605
606 return;
607
608err_free_gpio:
609 gpio_free(gpio);
610}
611
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300612#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
613#define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530614
615/**
616 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
617 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
618 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
619 * give 50MHz output for Eth0 and 1.
620 */
621static struct clk_synth cdce913_data = {
622 .id = 0x81,
623 .capacitor = 0x90,
624 .mux = 0x6d,
625 .pdiv2 = 0x2,
626 .pdiv3 = 0x2,
627};
628#endif
629
Sekhar Norif357b112018-08-23 17:11:30 +0530630#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
631 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
632
633#define MAX_CPSW_SLAVES 2
634
635/* At the moment, we do not want to stop booting for any failures here */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900636int ft_board_setup(void *fdt, struct bd_info *bd)
Sekhar Norif357b112018-08-23 17:11:30 +0530637{
638 const char *slave_path, *enet_name;
639 int enetnode, slavenode, phynode;
640 struct udevice *ethdev;
641 char alias[16];
642 u32 phy_id[2];
643 int phy_addr;
644 int i, ret;
645
646 /* phy address fixup needed only on beagle bone family */
647 if (!board_is_beaglebonex())
648 goto done;
649
650 for (i = 0; i < MAX_CPSW_SLAVES; i++) {
651 sprintf(alias, "ethernet%d", i);
652
653 slave_path = fdt_get_alias(fdt, alias);
654 if (!slave_path)
655 continue;
656
657 slavenode = fdt_path_offset(fdt, slave_path);
658 if (slavenode < 0)
659 continue;
660
661 enetnode = fdt_parent_offset(fdt, slavenode);
662 enet_name = fdt_get_name(fdt, enetnode, NULL);
663
664 ethdev = eth_get_dev_by_name(enet_name);
665 if (!ethdev)
666 continue;
667
668 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
669
670 /* check for phy_id as well as phy-handle properties */
671 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
672 phy_id, 2);
673 if (ret == 2) {
674 if (phy_id[1] != phy_addr) {
675 printf("fixing up phy_id for %s, old: %d, new: %d\n",
676 alias, phy_id[1], phy_addr);
677
678 phy_id[0] = cpu_to_fdt32(phy_id[0]);
679 phy_id[1] = cpu_to_fdt32(phy_addr);
680 do_fixup_by_path(fdt, slave_path, "phy_id",
681 phy_id, sizeof(phy_id), 0);
682 }
683 } else {
684 phynode = fdtdec_lookup_phandle(fdt, slavenode,
685 "phy-handle");
686 if (phynode < 0)
687 continue;
688
689 ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
690 if (ret < 0)
691 continue;
692
693 if (ret != phy_addr) {
694 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
695 alias, ret, phy_addr);
696
697 fdt_setprop_u32(fdt, phynode, "reg",
698 cpu_to_fdt32(phy_addr));
699 }
700 }
701 }
702
703done:
704 return 0;
705}
706#endif
707
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000708/*
709 * Basic board specific setup. Pinmux has been handled already.
710 */
711int board_init(void)
712{
Tom Rini303bfe82013-10-01 12:32:04 -0400713#if defined(CONFIG_HW_WATCHDOG)
714 hw_watchdog_init();
715#endif
716
Tom Rinif3b6a1d2013-08-09 11:22:13 -0400717 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Miquel Raynald0935362019-10-03 19:50:03 +0200718#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
Ilya Yanok3d9725e2012-11-06 13:06:31 +0000719 gpmc_init();
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400720#endif
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530721
Alex Kiernan20bba2e2018-04-01 09:22:37 +0000722#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
723 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530724 if (board_is_icev2()) {
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300725 int rv;
726 u32 reg;
727
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530728 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300729 /* Make J19 status available on GPIO1_26 */
730 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
731
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530732 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300733 /*
734 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
735 * jumpers near the port. Read the jumper value and set
736 * the pinmux, external mux and PHY clock accordingly.
737 * As jumper line is overridden by PHY RX_DV pin immediately
738 * after bootstrap (power-up/reset), we need to sample
739 * it during PHY reset using GPIO rising edge detection.
740 */
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530741 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300742 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
743 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
744 writel(reg, GPIO0_RISINGDETECT);
745 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
746 writel(reg, GPIO1_RISINGDETECT);
747 /* Reset PHYs to capture the Jumper setting */
748 gpio_set_value(GPIO_PHY_RESET, 0);
749 udelay(2); /* PHY datasheet states 1uS min. */
750 gpio_set_value(GPIO_PHY_RESET, 1);
751
752 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
753 if (reg) {
754 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
755 /* RMII mode */
756 printf("ETH0, CPSW\n");
757 } else {
758 /* MII mode */
759 printf("ETH0, PRU\n");
760 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
761 }
762
763 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
764 if (reg) {
765 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
766 /* RMII mode */
767 printf("ETH1, CPSW\n");
768 gpio_set_value(GPIO_MUX_MII_CTRL, 1);
769 } else {
770 /* MII mode */
771 printf("ETH1, PRU\n");
772 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
773 }
774
775 /* disable rising edge IRQs */
776 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
777 writel(reg, GPIO0_RISINGDETECT);
778 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
779 writel(reg, GPIO1_RISINGDETECT);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530780
781 rv = setup_clock_synthesizer(&cdce913_data);
782 if (rv) {
783 printf("Clock synthesizer setup failed %d\n", rv);
784 return rv;
785 }
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300786
787 /* reset PHYs */
788 gpio_set_value(GPIO_PHY_RESET, 0);
789 udelay(2); /* PHY datasheet states 1uS min. */
790 gpio_set_value(GPIO_PHY_RESET, 1);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530791 }
792#endif
793
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000794 return 0;
795}
796
Tom Rini40271852012-10-24 07:28:17 +0000797#ifdef CONFIG_BOARD_LATE_INIT
798int board_late_init(void)
799{
Tero Kristo67f79e72019-09-27 19:14:29 +0300800 struct udevice *dev;
Roger Quadros7c9d3782016-08-24 15:35:51 +0300801#if !defined(CONFIG_SPL_BUILD)
802 uint8_t mac_addr[6];
803 uint32_t mac_hi, mac_lo;
804#endif
805
Tom Rini40271852012-10-24 07:28:17 +0000806#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600807 char *name = NULL;
Tom Rini4021fd92013-07-18 15:13:01 -0400808
robertcnelson@gmail.comc5d7d222017-03-30 14:29:52 -0500809 if (board_is_bone_lt()) {
810 /* BeagleBoard.org BeagleBone Black Wireless: */
811 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
812 name = "BBBW";
813 }
robertcnelson@gmail.comb55cd7a2017-03-30 14:29:53 -0500814 /* SeeedStudio BeagleBone Green Wireless */
815 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
816 name = "BBGW";
817 }
robertcnelson@gmail.com89ef1d62017-03-30 14:29:54 -0500818 /* BeagleBoard.org BeagleBone Blue */
819 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
820 name = "BBBL";
821 }
robertcnelson@gmail.comc5d7d222017-03-30 14:29:52 -0500822 }
823
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600824 if (board_is_bbg1())
825 name = "BBG1";
Koen Kooi8a157862018-07-18 10:13:59 +0200826 if (board_is_bben())
827 name = "BBEN";
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600828 set_board_info_env(name);
Lokesh Vutla1eb0f542016-11-29 11:58:03 +0530829
830 /*
831 * Default FIT boot on HS devices. Non FIT images are not allowed
832 * on HS devices.
833 */
834 if (get_device_type() == HS_DEVICE)
Simon Glass6a38e412017-08-03 12:22:09 -0600835 env_set("boot_fit", "1");
Tom Rini40271852012-10-24 07:28:17 +0000836#endif
837
Roger Quadros7c9d3782016-08-24 15:35:51 +0300838#if !defined(CONFIG_SPL_BUILD)
839 /* try reading mac address from efuse */
840 mac_lo = readl(&cdev->macid0l);
841 mac_hi = readl(&cdev->macid0h);
842 mac_addr[0] = mac_hi & 0xFF;
843 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
844 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
845 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
846 mac_addr[4] = mac_lo & 0xFF;
847 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
848
Simon Glass64b723f2017-08-03 12:22:12 -0600849 if (!env_get("ethaddr")) {
Roger Quadros7c9d3782016-08-24 15:35:51 +0300850 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
851
852 if (is_valid_ethaddr(mac_addr))
Simon Glass8551d552017-08-03 12:22:11 -0600853 eth_env_set_enetaddr("ethaddr", mac_addr);
Roger Quadros7c9d3782016-08-24 15:35:51 +0300854 }
855
856 mac_lo = readl(&cdev->macid1l);
857 mac_hi = readl(&cdev->macid1h);
858 mac_addr[0] = mac_hi & 0xFF;
859 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
860 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
861 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
862 mac_addr[4] = mac_lo & 0xFF;
863 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
864
Simon Glass64b723f2017-08-03 12:22:12 -0600865 if (!env_get("eth1addr")) {
Roger Quadros7c9d3782016-08-24 15:35:51 +0300866 if (is_valid_ethaddr(mac_addr))
Simon Glass8551d552017-08-03 12:22:11 -0600867 eth_env_set_enetaddr("eth1addr", mac_addr);
Roger Quadros7c9d3782016-08-24 15:35:51 +0300868 }
869#endif
870
Sam Protsenkoa31ca622018-02-28 00:26:15 +0200871 if (!env_get("serial#")) {
872 char *board_serial = env_get("board_serial");
873 char *ethaddr = env_get("ethaddr");
874
875 if (!board_serial || !strncmp(board_serial, "unknown", 7))
876 env_set("serial#", ethaddr);
877 else
878 env_set("serial#", board_serial);
879 }
880
Tero Kristo67f79e72019-09-27 19:14:29 +0300881 /* Just probe the potentially supported cdce913 device */
Dario Binacchic2de9d42020-12-30 00:16:32 +0100882 uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
Tero Kristo67f79e72019-09-27 19:14:29 +0300883
Tom Rini40271852012-10-24 07:28:17 +0000884 return 0;
885}
886#endif
887
Simon Glass71fa5b42020-12-03 16:55:18 -0700888/* CPSW plat */
Faiz Abbas27866262019-03-18 13:54:37 +0530889#if !CONFIG_IS_ENABLED(OF_CONTROL)
890struct cpsw_slave_data slave_data[] = {
891 {
892 .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
893 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
894 .phy_addr = 0,
895 },
896 {
897 .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
898 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
899 .phy_addr = 1,
900 },
901};
902
903struct cpsw_platform_data am335_eth_data = {
904 .cpsw_base = CPSW_BASE,
905 .version = CPSW_CTRL_VERSION_2,
906 .bd_ram_ofs = CPSW_BD_OFFSET,
907 .ale_reg_ofs = CPSW_ALE_OFFSET,
908 .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
909 .mdio_div = CPSW_MDIO_DIV,
910 .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
911 .channels = 8,
912 .slaves = 2,
913 .slave_data = slave_data,
914 .ale_entries = 1024,
Faiz Abbas27866262019-03-18 13:54:37 +0530915 .mac_control = 0x20,
916 .active_slave = 0,
917 .mdio_base = 0x4a101000,
918 .gmii_sel = 0x44e10650,
919 .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
920 .syscon_addr = 0x44e10630,
921 .macid_sel_compat = "cpsw,am33xx",
922};
923
924struct eth_pdata cpsw_pdata = {
925 .iobase = 0x4a100000,
926 .phy_interface = 0,
927 .priv_pdata = &am335_eth_data,
928};
929
Simon Glass1d8364a2020-12-28 20:34:54 -0700930U_BOOT_DRVINFO(am335x_eth) = {
Faiz Abbas27866262019-03-18 13:54:37 +0530931 .name = "eth_cpsw",
Simon Glass71fa5b42020-12-03 16:55:18 -0700932 .plat = &cpsw_pdata,
Faiz Abbas27866262019-03-18 13:54:37 +0530933};
934#endif
935
Lokesh Vutla89b9f302016-05-16 11:24:24 +0530936#ifdef CONFIG_SPL_LOAD_FIT
937int board_fit_config_name_match(const char *name)
938{
939 if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
940 return 0;
941 else if (board_is_bone() && !strcmp(name, "am335x-bone"))
942 return 0;
943 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
944 return 0;
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500945 else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
946 return 0;
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530947 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
948 return 0;
Lokesh Vutla1edfcaf2016-05-16 11:24:29 +0530949 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
950 return 0;
Lokesh Vutla7ecf1962016-05-16 11:47:28 +0530951 else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
952 return 0;
Lokesh Vutla89b9f302016-05-16 11:24:24 +0530953 else
954 return -1;
955}
956#endif
Andrew F. Davisbd249152016-08-30 14:06:24 -0500957
958#ifdef CONFIG_TI_SECURE_DEVICE
959void board_fit_image_post_process(void **p_image, size_t *p_size)
960{
961 secure_boot_verify_image(p_image, p_size);
962}
963#endif
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530964
965#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glassb75b15b2020-12-03 16:55:23 -0700966static const struct omap_hsmmc_plat am335x_mmc0_plat = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530967 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
968 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
969 .cfg.f_min = 400000,
970 .cfg.f_max = 52000000,
971 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
972 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
973};
974
Simon Glass1d8364a2020-12-28 20:34:54 -0700975U_BOOT_DRVINFO(am335x_mmc0) = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530976 .name = "omap_hsmmc",
Simon Glassb75b15b2020-12-03 16:55:23 -0700977 .plat = &am335x_mmc0_plat,
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530978};
979
Simon Glassb75b15b2020-12-03 16:55:23 -0700980static const struct omap_hsmmc_plat am335x_mmc1_plat = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530981 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
982 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
983 .cfg.f_min = 400000,
984 .cfg.f_max = 52000000,
985 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
986 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
987};
988
Simon Glass1d8364a2020-12-28 20:34:54 -0700989U_BOOT_DRVINFO(am335x_mmc1) = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530990 .name = "omap_hsmmc",
Simon Glassb75b15b2020-12-03 16:55:23 -0700991 .plat = &am335x_mmc1_plat,
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530992};
993#endif