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git01.mediatek.com / filogic / uboot / d6f87ac3eaac3a187faaf4f0b8394850dda8ac60 / . / dts / upstream / src / arm64 / qcom / sm6350.dtsi
blob: 84ff20a96c838b52d8e5d54f97e3792de3f8fd99 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
5 */
6
7#include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8#include <dt-bindings/clock/qcom,gcc-sm6350.h>
9#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
10#include <dt-bindings/clock/qcom,rpmh.h>
11#include <dt-bindings/clock/qcom,sm6350-camcc.h>
12#include <dt-bindings/dma/qcom-gpi.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interconnect/qcom,icc.h>
15#include <dt-bindings/interconnect/qcom,osm-l3.h>
16#include <dt-bindings/interconnect/qcom,sm6350.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include <dt-bindings/mailbox/qcom-ipcc.h>
19#include <dt-bindings/phy/phy-qcom-qmp.h>
20#include <dt-bindings/power/qcom-rpmpd.h>
21#include <dt-bindings/soc/qcom,rpmh-rsc.h>
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]22#include <dt-bindings/thermal/thermal.h>
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]23
24/ {
25 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 clocks {
30 xo_board: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <76800000>;
34 clock-output-names = "xo_board";
35 };
36
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 clock-frequency = <32764>;
40 #clock-cells = <0>;
41 };
42 };
43
44 cpus {
45 #address-cells = <2>;
46 #size-cells = <0>;
47
48 CPU0: cpu@0 {
49 device_type = "cpu";
50 compatible = "qcom,kryo560";
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
53 enable-method = "psci";
54 capacity-dmips-mhz = <1024>;
55 dynamic-power-coefficient = <100>;
56 next-level-cache = <&L2_0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
58 operating-points-v2 = <&cpu0_opp_table>;
59 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
60 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
62 power-domains = <&CPU_PD0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
66 compatible = "cache";
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "cache";
72 cache-level = <3>;
73 cache-unified;
74 };
75 };
76 };
77
78 CPU1: cpu@100 {
79 device_type = "cpu";
80 compatible = "qcom,kryo560";
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
83 enable-method = "psci";
84 capacity-dmips-mhz = <1024>;
85 dynamic-power-coefficient = <100>;
86 next-level-cache = <&L2_100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 operating-points-v2 = <&cpu0_opp_table>;
89 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
90 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
91 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
92 power-domains = <&CPU_PD1>;
93 power-domain-names = "psci";
94 #cooling-cells = <2>;
95 L2_100: l2-cache {
96 compatible = "cache";
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
100 };
101 };
102
103 CPU2: cpu@200 {
104 device_type = "cpu";
105 compatible = "qcom,kryo560";
106 reg = <0x0 0x200>;
107 clocks = <&cpufreq_hw 0>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <1024>;
110 dynamic-power-coefficient = <100>;
111 next-level-cache = <&L2_200>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <&cpu0_opp_table>;
114 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
115 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
116 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_PD2>;
118 power-domain-names = "psci";
119 #cooling-cells = <2>;
120 L2_200: l2-cache {
121 compatible = "cache";
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&L3_0>;
125 };
126 };
127
128 CPU3: cpu@300 {
129 device_type = "cpu";
130 compatible = "qcom,kryo560";
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 dynamic-power-coefficient = <100>;
136 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
140 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
142 power-domains = <&CPU_PD3>;
143 power-domain-names = "psci";
144 #cooling-cells = <2>;
145 L2_300: l2-cache {
146 compatible = "cache";
147 cache-level = <2>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
150 };
151 };
152
153 CPU4: cpu@400 {
154 device_type = "cpu";
155 compatible = "qcom,kryo560";
156 reg = <0x0 0x400>;
157 clocks = <&cpufreq_hw 0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 dynamic-power-coefficient = <100>;
161 next-level-cache = <&L2_400>;
162 qcom,freq-domain = <&cpufreq_hw 0>;
163 operating-points-v2 = <&cpu0_opp_table>;
164 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
165 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
167 power-domains = <&CPU_PD4>;
168 power-domain-names = "psci";
169 #cooling-cells = <2>;
170 L2_400: l2-cache {
171 compatible = "cache";
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&L3_0>;
175 };
176 };
177
178 CPU5: cpu@500 {
179 device_type = "cpu";
180 compatible = "qcom,kryo560";
181 reg = <0x0 0x500>;
182 clocks = <&cpufreq_hw 0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <1024>;
185 dynamic-power-coefficient = <100>;
186 next-level-cache = <&L2_500>;
187 qcom,freq-domain = <&cpufreq_hw 0>;
188 operating-points-v2 = <&cpu0_opp_table>;
189 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
190 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
192 power-domains = <&CPU_PD5>;
193 power-domain-names = "psci";
194 #cooling-cells = <2>;
195 L2_500: l2-cache {
196 compatible = "cache";
197 cache-level = <2>;
198 cache-unified;
199 next-level-cache = <&L3_0>;
200 };
201 };
202
203 CPU6: cpu@600 {
204 device_type = "cpu";
205 compatible = "qcom,kryo560";
206 reg = <0x0 0x600>;
207 clocks = <&cpufreq_hw 1>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1894>;
210 dynamic-power-coefficient = <703>;
211 next-level-cache = <&L2_600>;
212 qcom,freq-domain = <&cpufreq_hw 1>;
213 operating-points-v2 = <&cpu6_opp_table>;
214 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
215 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
216 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
217 power-domains = <&CPU_PD6>;
218 power-domain-names = "psci";
219 #cooling-cells = <2>;
220 L2_600: l2-cache {
221 compatible = "cache";
222 cache-level = <2>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
225 };
226 };
227
228 CPU7: cpu@700 {
229 device_type = "cpu";
230 compatible = "qcom,kryo560";
231 reg = <0x0 0x700>;
232 clocks = <&cpufreq_hw 1>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1894>;
235 dynamic-power-coefficient = <703>;
236 next-level-cache = <&L2_700>;
237 qcom,freq-domain = <&cpufreq_hw 1>;
238 operating-points-v2 = <&cpu6_opp_table>;
239 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
240 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
241 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
242 power-domains = <&CPU_PD7>;
243 power-domain-names = "psci";
244 #cooling-cells = <2>;
245 L2_700: l2-cache {
246 compatible = "cache";
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
250 };
251 };
252
253 cpu-map {
254 cluster0 {
255 core0 {
256 cpu = <&CPU0>;
257 };
258
259 core1 {
260 cpu = <&CPU1>;
261 };
262
263 core2 {
264 cpu = <&CPU2>;
265 };
266
267 core3 {
268 cpu = <&CPU3>;
269 };
270
271 core4 {
272 cpu = <&CPU4>;
273 };
274
275 core5 {
276 cpu = <&CPU5>;
277 };
278
279 core6 {
280 cpu = <&CPU6>;
281 };
282
283 core7 {
284 cpu = <&CPU7>;
285 };
286 };
287 };
288
289 domain-idle-states {
290 CLUSTER_SLEEP_PC: cluster-sleep-0 {
291 compatible = "domain-idle-state";
292 arm,psci-suspend-param = <0x41000044>;
293 entry-latency-us = <2752>;
294 exit-latency-us = <3048>;
295 min-residency-us = <6118>;
296 };
297
298 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
299 compatible = "domain-idle-state";
300 arm,psci-suspend-param = <0x41001244>;
301 entry-latency-us = <3638>;
302 exit-latency-us = <4562>;
303 min-residency-us = <8467>;
304 };
305
306 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
307 compatible = "domain-idle-state";
308 arm,psci-suspend-param = <0x4100b244>;
309 entry-latency-us = <3263>;
310 exit-latency-us = <6562>;
311 min-residency-us = <9987>;
312 };
313 };
314
315 cpu_idle_states: idle-states {
316 entry-method = "psci";
317
318 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "little-power-collapse";
321 arm,psci-suspend-param = <0x40000003>;
322 entry-latency-us = <549>;
323 exit-latency-us = <901>;
324 min-residency-us = <1774>;
325 local-timer-stop;
326 };
327
328 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
329 compatible = "arm,idle-state";
330 idle-state-name = "little-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <702>;
333 exit-latency-us = <915>;
334 min-residency-us = <4001>;
335 local-timer-stop;
336 };
337
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "big-power-collapse";
341 arm,psci-suspend-param = <0x40000003>;
342 entry-latency-us = <523>;
343 exit-latency-us = <1244>;
344 min-residency-us = <2207>;
345 local-timer-stop;
346 };
347
348 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
349 compatible = "arm,idle-state";
350 idle-state-name = "big-rail-power-collapse";
351 arm,psci-suspend-param = <0x40000004>;
352 entry-latency-us = <526>;
353 exit-latency-us = <1854>;
354 min-residency-us = <5555>;
355 local-timer-stop;
356 };
357 };
358 };
359
360 firmware {
361 scm: scm {
362 compatible = "qcom,scm-sm6350", "qcom,scm";
363 #reset-cells = <1>;
364 };
365 };
366
367 memory@80000000 {
368 device_type = "memory";
369 /* We expect the bootloader to fill in the size */
370 reg = <0x0 0x80000000 0x0 0x0>;
371 };
372
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points-v2";
375 opp-shared;
376
377 opp-300000000 {
378 opp-hz = /bits/ 64 <300000000>;
379 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
380 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
381 };
382
383 opp-576000000 {
384 opp-hz = /bits/ 64 <576000000>;
385 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
386 };
387
388 opp-768000000 {
389 opp-hz = /bits/ 64 <768000000>;
390 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
391 };
392
393 opp-1017600000 {
394 opp-hz = /bits/ 64 <1017600000>;
395 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
396 };
397
398 opp-1248000000 {
399 opp-hz = /bits/ 64 <1248000000>;
400 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
401 };
402
403 opp-1324800000 {
404 opp-hz = /bits/ 64 <1324800000>;
405 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
406 };
407
408 opp-1516800000 {
409 opp-hz = /bits/ 64 <1516800000>;
410 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
411 };
412
413 opp-1612800000 {
414 opp-hz = /bits/ 64 <1612800000>;
415 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
416 };
417
418 opp-1708800000 {
419 opp-hz = /bits/ 64 <1708800000>;
420 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
421 };
422 };
423
424 cpu6_opp_table: opp-table-cpu6 {
425 compatible = "operating-points-v2";
426 opp-shared;
427
428 opp-300000000 {
429 opp-hz = /bits/ 64 <300000000>;
430 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
431 };
432
433 opp-787200000 {
434 opp-hz = /bits/ 64 <787200000>;
435 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
436 };
437
438 opp-979200000 {
439 opp-hz = /bits/ 64 <979200000>;
440 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
441 };
442
443 opp-1036800000 {
444 opp-hz = /bits/ 64 <1036800000>;
445 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
446 };
447
448 opp-1248000000 {
449 opp-hz = /bits/ 64 <1248000000>;
450 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
451 };
452
453 opp-1401600000 {
454 opp-hz = /bits/ 64 <1401600000>;
455 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
456 };
457
458 opp-1555200000 {
459 opp-hz = /bits/ 64 <1555200000>;
460 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
461 };
462
463 opp-1766400000 {
464 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
466 };
467
468 opp-1900800000 {
469 opp-hz = /bits/ 64 <1900800000>;
470 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
471 };
472
473 opp-2073600000 {
474 opp-hz = /bits/ 64 <2073600000>;
475 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
476 };
477 };
478
479 qup_opp_table: opp-table-qup {
480 compatible = "operating-points-v2";
481
482 opp-75000000 {
483 opp-hz = /bits/ 64 <75000000>;
484 required-opps = <&rpmhpd_opp_low_svs>;
485 };
486
487 opp-100000000 {
488 opp-hz = /bits/ 64 <100000000>;
489 required-opps = <&rpmhpd_opp_svs>;
490 };
491
492 opp-128000000 {
493 opp-hz = /bits/ 64 <128000000>;
494 required-opps = <&rpmhpd_opp_nom>;
495 };
496 };
497
498 pmu {
499 compatible = "arm,armv8-pmuv3";
500 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
501 };
502
503 psci {
504 compatible = "arm,psci-1.0";
505 method = "smc";
506
507 CPU_PD0: power-domain-cpu0 {
508 #power-domain-cells = <0>;
509 power-domains = <&CLUSTER_PD>;
510 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
511 };
512
513 CPU_PD1: power-domain-cpu1 {
514 #power-domain-cells = <0>;
515 power-domains = <&CLUSTER_PD>;
516 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
517 };
518
519 CPU_PD2: power-domain-cpu2 {
520 #power-domain-cells = <0>;
521 power-domains = <&CLUSTER_PD>;
522 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
523 };
524
525 CPU_PD3: power-domain-cpu3 {
526 #power-domain-cells = <0>;
527 power-domains = <&CLUSTER_PD>;
528 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
529 };
530
531 CPU_PD4: power-domain-cpu4 {
532 #power-domain-cells = <0>;
533 power-domains = <&CLUSTER_PD>;
534 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
535 };
536
537 CPU_PD5: power-domain-cpu5 {
538 #power-domain-cells = <0>;
539 power-domains = <&CLUSTER_PD>;
540 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
541 };
542
543 CPU_PD6: power-domain-cpu6 {
544 #power-domain-cells = <0>;
545 power-domains = <&CLUSTER_PD>;
546 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
547 };
548
549 CPU_PD7: power-domain-cpu7 {
550 #power-domain-cells = <0>;
551 power-domains = <&CLUSTER_PD>;
552 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
553 };
554
555 CLUSTER_PD: power-domain-cpu-cluster0 {
556 #power-domain-cells = <0>;
557 domain-idle-states = <&CLUSTER_SLEEP_PC
558 &CLUSTER_SLEEP_CX_RET
559 &CLUSTER_AOSS_SLEEP>;
560 };
561 };
562
563 reserved_memory: reserved-memory {
564 #address-cells = <2>;
565 #size-cells = <2>;
566 ranges;
567
568 hyp_mem: memory@80000000 {
569 reg = <0 0x80000000 0 0x600000>;
570 no-map;
571 };
572
573 xbl_aop_mem: memory@80700000 {
574 reg = <0 0x80700000 0 0x160000>;
575 no-map;
576 };
577
578 cmd_db: memory@80860000 {
579 compatible = "qcom,cmd-db";
580 reg = <0 0x80860000 0 0x20000>;
581 no-map;
582 };
583
584 sec_apps_mem: memory@808ff000 {
585 reg = <0 0x808ff000 0 0x1000>;
586 no-map;
587 };
588
589 smem_mem: memory@80900000 {
590 reg = <0 0x80900000 0 0x200000>;
591 no-map;
592 };
593
594 cdsp_sec_mem: memory@80b00000 {
595 reg = <0 0x80b00000 0 0x1e00000>;
596 no-map;
597 };
598
599 pil_camera_mem: memory@86000000 {
600 reg = <0 0x86000000 0 0x500000>;
601 no-map;
602 };
603
604 pil_npu_mem: memory@86500000 {
605 reg = <0 0x86500000 0 0x500000>;
606 no-map;
607 };
608
609 pil_video_mem: memory@86a00000 {
610 reg = <0 0x86a00000 0 0x500000>;
611 no-map;
612 };
613
614 pil_cdsp_mem: memory@86f00000 {
615 reg = <0 0x86f00000 0 0x1e00000>;
616 no-map;
617 };
618
619 pil_adsp_mem: memory@88d00000 {
620 reg = <0 0x88d00000 0 0x2800000>;
621 no-map;
622 };
623
624 wlan_fw_mem: memory@8b500000 {
625 reg = <0 0x8b500000 0 0x200000>;
626 no-map;
627 };
628
629 pil_ipa_fw_mem: memory@8b700000 {
630 reg = <0 0x8b700000 0 0x10000>;
631 no-map;
632 };
633
634 pil_ipa_gsi_mem: memory@8b710000 {
635 reg = <0 0x8b710000 0 0x5400>;
636 no-map;
637 };
638
639 pil_modem_mem: memory@8b800000 {
640 reg = <0 0x8b800000 0 0xf800000>;
641 no-map;
642 };
643
644 cont_splash_memory: memory@a0000000 {
645 reg = <0 0xa0000000 0 0x2300000>;
646 no-map;
647 };
648
649 dfps_data_memory: memory@a2300000 {
650 reg = <0 0xa2300000 0 0x100000>;
651 no-map;
652 };
653
654 removed_region: memory@c0000000 {
655 reg = <0 0xc0000000 0 0x3900000>;
656 no-map;
657 };
658
659 pil_gpu_mem: memory@f0d00000 {
660 reg = <0 0xf0d00000 0 0x1000>;
661 no-map;
662 };
663
664 debug_region: memory@ffb00000 {
665 reg = <0 0xffb00000 0 0xc0000>;
666 no-map;
667 };
668
669 last_log_region: memory@ffbc0000 {
670 reg = <0 0xffbc0000 0 0x40000>;
671 no-map;
672 };
673
674 ramoops: ramoops@ffc00000 {
675 compatible = "ramoops";
676 reg = <0 0xffc00000 0 0x100000>;
677 record-size = <0x1000>;
678 console-size = <0x40000>;
679 pmsg-size = <0x20000>;
680 ecc-size = <16>;
681 no-map;
682 };
683
684 cmdline_region: memory@ffd00000 {
685 reg = <0 0xffd00000 0 0x1000>;
686 no-map;
687 };
688 };
689
690 smem {
691 compatible = "qcom,smem";
692 memory-region = <&smem_mem>;
693 hwlocks = <&tcsr_mutex 3>;
694 };
695
696 smp2p-adsp {
697 compatible = "qcom,smp2p";
698 qcom,smem = <443>, <429>;
699 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
700 IPCC_MPROC_SIGNAL_SMP2P
701 IRQ_TYPE_EDGE_RISING>;
702 mboxes = <&ipcc IPCC_CLIENT_LPASS
703 IPCC_MPROC_SIGNAL_SMP2P>;
704
705 qcom,local-pid = <0>;
706 qcom,remote-pid = <2>;
707
708 smp2p_adsp_out: master-kernel {
709 qcom,entry-name = "master-kernel";
710 #qcom,smem-state-cells = <1>;
711 };
712
713 smp2p_adsp_in: slave-kernel {
714 qcom,entry-name = "slave-kernel";
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 };
718 };
719
720 smp2p-cdsp {
721 compatible = "qcom,smp2p";
722 qcom,smem = <94>, <432>;
723 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
724 IPCC_MPROC_SIGNAL_SMP2P
725 IRQ_TYPE_EDGE_RISING>;
726 mboxes = <&ipcc IPCC_CLIENT_CDSP
727 IPCC_MPROC_SIGNAL_SMP2P>;
728
729 qcom,local-pid = <0>;
730 qcom,remote-pid = <5>;
731
732 smp2p_cdsp_out: master-kernel {
733 qcom,entry-name = "master-kernel";
734 #qcom,smem-state-cells = <1>;
735 };
736
737 smp2p_cdsp_in: slave-kernel {
738 qcom,entry-name = "slave-kernel";
739 interrupt-controller;
740 #interrupt-cells = <2>;
741 };
742 };
743
744 smp2p-mpss {
745 compatible = "qcom,smp2p";
746 qcom,smem = <435>, <428>;
747
748 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
749 IPCC_MPROC_SIGNAL_SMP2P
750 IRQ_TYPE_EDGE_RISING>;
751 mboxes = <&ipcc IPCC_CLIENT_MPSS
752 IPCC_MPROC_SIGNAL_SMP2P>;
753
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>;
756
757 modem_smp2p_out: master-kernel {
758 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells = <1>;
760 };
761
762 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "slave-kernel";
764 interrupt-controller;
765 #interrupt-cells = <2>;
766 };
767
768 ipa_smp2p_out: ipa-ap-to-modem {
769 qcom,entry-name = "ipa";
770 #qcom,smem-state-cells = <1>;
771 };
772
773 ipa_smp2p_in: ipa-modem-to-ap {
774 qcom,entry-name = "ipa";
775 interrupt-controller;
776 #interrupt-cells = <2>;
777 };
778 };
779
780 soc: soc@0 {
781 #address-cells = <2>;
782 #size-cells = <2>;
783 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus";
786
787 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc-sm6350";
789 reg = <0 0x00100000 0 0x1f0000>;
790 #clock-cells = <1>;
791 #reset-cells = <1>;
792 #power-domain-cells = <1>;
793 clock-names = "bi_tcxo",
794 "bi_tcxo_ao",
795 "sleep_clk";
796 clocks = <&rpmhcc RPMH_CXO_CLK>,
797 <&rpmhcc RPMH_CXO_CLK_A>,
798 <&sleep_clk>;
799 };
800
801 ipcc: mailbox@408000 {
802 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
803 reg = <0 0x00408000 0 0x1000>;
804 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
805 interrupt-controller;
806 #interrupt-cells = <3>;
807 #mbox-cells = <2>;
808 };
809
810 qfprom: qfprom@784000 {
811 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
812 reg = <0 0x00784000 0 0x3000>;
813 #address-cells = <1>;
814 #size-cells = <1>;
815
816 gpu_speed_bin: gpu-speed-bin@2015 {
817 reg = <0x2015 0x1>;
818 bits = <0 8>;
819 };
820 };
821
822 rng: rng@793000 {
823 compatible = "qcom,prng-ee";
824 reg = <0 0x00793000 0 0x1000>;
825 clocks = <&gcc GCC_PRNG_AHB_CLK>;
826 clock-names = "core";
827 };
828
829 sdhc_1: mmc@7c4000 {
830 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
831 reg = <0 0x007c4000 0 0x1000>,
832 <0 0x007c5000 0 0x1000>,
833 <0 0x007c8000 0 0x8000>;
834 reg-names = "hc", "cqhci", "ice";
835
836 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
838 interrupt-names = "hc_irq", "pwr_irq";
839 iommus = <&apps_smmu 0x60 0x0>;
840
841 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
842 <&gcc GCC_SDCC1_APPS_CLK>,
843 <&rpmhcc RPMH_CXO_CLK>;
844 clock-names = "iface", "core", "xo";
845 resets = <&gcc GCC_SDCC1_BCR>;
846 qcom,dll-config = <0x000f642c>;
847 qcom,ddr-config = <0x80040868>;
848 power-domains = <&rpmhpd SM6350_CX>;
849 operating-points-v2 = <&sdhc1_opp_table>;
850 bus-width = <8>;
851 non-removable;
852 supports-cqe;
853
854 status = "disabled";
855
856 sdhc1_opp_table: opp-table {
857 compatible = "operating-points-v2";
858
859 opp-19200000 {
860 opp-hz = /bits/ 64 <19200000>;
861 required-opps = <&rpmhpd_opp_min_svs>;
862 };
863
864 opp-100000000 {
865 opp-hz = /bits/ 64 <100000000>;
866 required-opps = <&rpmhpd_opp_low_svs>;
867 };
868
869 opp-384000000 {
870 opp-hz = /bits/ 64 <384000000>;
871 required-opps = <&rpmhpd_opp_svs_l1>;
872 };
873 };
874 };
875
876 gpi_dma0: dma-controller@800000 {
877 compatible = "qcom,sm6350-gpi-dma";
878 reg = <0 0x00800000 0 0x60000>;
879 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
889 dma-channels = <10>;
890 dma-channel-mask = <0x1f>;
891 iommus = <&apps_smmu 0x56 0x0>;
892 #dma-cells = <3>;
893 status = "disabled";
894 };
895
896 qupv3_id_0: geniqup@8c0000 {
897 compatible = "qcom,geni-se-qup";
898 reg = <0x0 0x008c0000 0x0 0x2000>;
899 clock-names = "m-ahb", "s-ahb";
900 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
901 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
902 #address-cells = <2>;
903 #size-cells = <2>;
904 iommus = <&apps_smmu 0x43 0x0>;
905 ranges;
906 status = "disabled";
907
908 i2c0: i2c@880000 {
909 compatible = "qcom,geni-i2c";
910 reg = <0 0x00880000 0 0x4000>;
911 clock-names = "se";
912 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
913 pinctrl-names = "default";
914 pinctrl-0 = <&qup_i2c0_default>;
915 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
916 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
917 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
918 dma-names = "tx", "rx";
919 #address-cells = <1>;
920 #size-cells = <0>;
921 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
922 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
923 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
924 interconnect-names = "qup-core", "qup-config", "qup-memory";
925 status = "disabled";
926 };
927
928 uart1: serial@884000 {
929 compatible = "qcom,geni-uart";
930 reg = <0 0x00884000 0 0x4000>;
931 clock-names = "se";
932 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
935 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
936 power-domains = <&rpmhpd SM6350_CX>;
937 operating-points-v2 = <&qup_opp_table>;
938 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
939 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
940 interconnect-names = "qup-core", "qup-config";
941 status = "disabled";
942 };
943
944 i2c2: i2c@888000 {
945 compatible = "qcom,geni-i2c";
946 reg = <0 0x00888000 0 0x4000>;
947 clock-names = "se";
948 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&qup_i2c2_default>;
951 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
952 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
953 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
954 dma-names = "tx", "rx";
955 #address-cells = <1>;
956 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
959 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
961 status = "disabled";
962 };
963 };
964
965 gpi_dma1: dma-controller@900000 {
966 compatible = "qcom,sm6350-gpi-dma";
967 reg = <0 0x00900000 0 0x60000>;
968 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
978 dma-channels = <10>;
979 dma-channel-mask = <0x3f>;
980 iommus = <&apps_smmu 0x4d6 0x0>;
981 #dma-cells = <3>;
982 status = "disabled";
983 };
984
985 qupv3_id_1: geniqup@9c0000 {
986 compatible = "qcom,geni-se-qup";
987 reg = <0x0 0x009c0000 0x0 0x2000>;
988 clock-names = "m-ahb", "s-ahb";
989 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
990 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
991 #address-cells = <2>;
992 #size-cells = <2>;
993 iommus = <&apps_smmu 0x4c3 0x0>;
994 ranges;
995 status = "disabled";
996
997 i2c6: i2c@980000 {
998 compatible = "qcom,geni-i2c";
999 reg = <0 0x00980000 0 0x4000>;
1000 clock-names = "se";
1001 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_i2c6_default>;
1004 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1005 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1006 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1007 dma-names = "tx", "rx";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1012 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1014 status = "disabled";
1015 };
1016
1017 i2c7: i2c@984000 {
1018 compatible = "qcom,geni-i2c";
1019 reg = <0 0x00984000 0 0x4000>;
1020 clock-names = "se";
1021 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_i2c7_default>;
1024 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1025 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1026 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1027 dma-names = "tx", "rx";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1031 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1032 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1034 status = "disabled";
1035 };
1036
1037 i2c8: i2c@988000 {
1038 compatible = "qcom,geni-i2c";
1039 reg = <0 0x00988000 0 0x4000>;
1040 clock-names = "se";
1041 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&qup_i2c8_default>;
1044 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1045 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1046 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1047 dma-names = "tx", "rx";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1052 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1054 status = "disabled";
1055 };
1056
1057 uart9: serial@98c000 {
1058 compatible = "qcom,geni-debug-uart";
1059 reg = <0 0x0098c000 0 0x4000>;
1060 clock-names = "se";
1061 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_uart9_default>;
1064 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1065 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1067 interconnect-names = "qup-core", "qup-config";
1068 status = "disabled";
1069 };
1070
1071 i2c10: i2c@990000 {
1072 compatible = "qcom,geni-i2c";
1073 reg = <0 0x00990000 0 0x4000>;
1074 clock-names = "se";
1075 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c10_default>;
1078 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1079 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1080 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1081 dma-names = "tx", "rx";
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1085 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1086 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1087 interconnect-names = "qup-core", "qup-config", "qup-memory";
1088 status = "disabled";
1089 };
1090 };
1091
1092 config_noc: interconnect@1500000 {
1093 compatible = "qcom,sm6350-config-noc";
1094 reg = <0 0x01500000 0 0x28000>;
1095 #interconnect-cells = <2>;
1096 qcom,bcm-voters = <&apps_bcm_voter>;
1097 };
1098
1099 system_noc: interconnect@1620000 {
1100 compatible = "qcom,sm6350-system-noc";
1101 reg = <0 0x01620000 0 0x17080>;
1102 #interconnect-cells = <2>;
1103 qcom,bcm-voters = <&apps_bcm_voter>;
1104
1105 clk_virt: interconnect-clk-virt {
1106 compatible = "qcom,sm6350-clk-virt";
1107 #interconnect-cells = <2>;
1108 qcom,bcm-voters = <&apps_bcm_voter>;
1109 };
1110 };
1111
1112 aggre1_noc: interconnect@16e0000 {
1113 compatible = "qcom,sm6350-aggre1-noc";
1114 reg = <0 0x016e0000 0 0x15080>;
1115 #interconnect-cells = <2>;
1116 qcom,bcm-voters = <&apps_bcm_voter>;
1117 };
1118
1119 aggre2_noc: interconnect@1700000 {
1120 compatible = "qcom,sm6350-aggre2-noc";
1121 reg = <0 0x01700000 0 0x1f880>;
1122 #interconnect-cells = <2>;
1123 qcom,bcm-voters = <&apps_bcm_voter>;
1124
1125 compute_noc: interconnect-compute-noc {
1126 compatible = "qcom,sm6350-compute-noc";
1127 #interconnect-cells = <2>;
1128 qcom,bcm-voters = <&apps_bcm_voter>;
1129 };
1130 };
1131
1132 mmss_noc: interconnect@1740000 {
1133 compatible = "qcom,sm6350-mmss-noc";
1134 reg = <0 0x01740000 0 0x1c100>;
1135 #interconnect-cells = <2>;
1136 qcom,bcm-voters = <&apps_bcm_voter>;
1137 };
1138
1139 ufs_mem_hc: ufs@1d84000 {
1140 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1141 "jedec,ufs-2.0";
1142 reg = <0 0x01d84000 0 0x3000>,
1143 <0 0x01d90000 0 0x8000>;
1144 reg-names = "std", "ice";
1145 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1146 phys = <&ufs_mem_phy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1147 phy-names = "ufsphy";
1148 lanes-per-direction = <2>;
1149 #reset-cells = <1>;
1150 resets = <&gcc GCC_UFS_PHY_BCR>;
1151 reset-names = "rst";
1152
1153 power-domains = <&gcc UFS_PHY_GDSC>;
1154
1155 iommus = <&apps_smmu 0x80 0x0>;
1156
1157 clock-names = "core_clk",
1158 "bus_aggr_clk",
1159 "iface_clk",
1160 "core_clk_unipro",
1161 "ref_clk",
1162 "tx_lane0_sync_clk",
1163 "rx_lane0_sync_clk",
1164 "rx_lane1_sync_clk",
1165 "ice_core_clk";
1166 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1167 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1168 <&gcc GCC_UFS_PHY_AHB_CLK>,
1169 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1170 <&rpmhcc RPMH_QLINK_CLK>,
1171 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1172 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1173 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
1174 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1175 freq-table-hz =
1176 <50000000 200000000>,
1177 <0 0>,
1178 <0 0>,
1179 <37500000 150000000>,
1180 <75000000 300000000>,
1181 <0 0>,
1182 <0 0>,
1183 <0 0>,
1184 <0 0>;
1185
1186 status = "disabled";
1187 };
1188
1189 ufs_mem_phy: phy@1d87000 {
1190 compatible = "qcom,sm6350-qmp-ufs-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1191 reg = <0 0x01d87000 0 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1192
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1193 clocks = <&rpmhcc RPMH_CXO_CLK>,
1194 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1195 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1196 clock-names = "ref",
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1197 "ref_aux",
1198 "qref";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1199
1200 resets = <&ufs_mem_hc 0>;
1201 reset-names = "ufsphy";
1202
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1203 #phy-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1204
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1205 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1206 };
1207
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1208 cryptobam: dma-controller@1dc4000 {
1209 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1210 reg = <0 0x01dc4000 0 0x24000>;
1211 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1212 #dma-cells = <1>;
1213 qcom,ee = <0>;
1214 qcom,controlled-remotely;
1215 num-channels = <16>;
1216 qcom,num-ees = <4>;
1217 iommus = <&apps_smmu 0x426 0x11>,
1218 <&apps_smmu 0x432 0x0>,
1219 <&apps_smmu 0x436 0x11>,
1220 <&apps_smmu 0x438 0x1>,
1221 <&apps_smmu 0x43f 0x0>;
1222 };
1223
1224 crypto: crypto@1dfa000 {
1225 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
1226 reg = <0 0x01dfa000 0 0x6000>;
1227 dmas = <&cryptobam 4>, <&cryptobam 5>;
1228 dma-names = "rx", "tx";
1229 iommus = <&apps_smmu 0x426 0x11>,
1230 <&apps_smmu 0x432 0x0>,
1231 <&apps_smmu 0x436 0x11>,
1232 <&apps_smmu 0x438 0x1>,
1233 <&apps_smmu 0x43f 0x0>;
1234 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS
1235 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>;
1236 interconnect-names = "memory";
1237 };
1238
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1239 ipa: ipa@1e40000 {
1240 compatible = "qcom,sm6350-ipa";
1241
1242 iommus = <&apps_smmu 0x440 0x0>,
1243 <&apps_smmu 0x442 0x0>;
1244 reg = <0 0x01e40000 0 0x8000>,
1245 <0 0x01e50000 0 0x3000>,
1246 <0 0x01e04000 0 0x23000>;
1247 reg-names = "ipa-reg",
1248 "ipa-shared",
1249 "gsi";
1250
1251 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1252 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1253 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1254 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1255 interrupt-names = "ipa",
1256 "gsi",
1257 "ipa-clock-query",
1258 "ipa-setup-ready";
1259
1260 clocks = <&rpmhcc RPMH_IPA_CLK>;
1261 clock-names = "core";
1262
1263 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>,
1264 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>,
1265 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>;
1266 interconnect-names = "memory", "imem", "config";
1267
1268 qcom,smem-states = <&ipa_smp2p_out 0>,
1269 <&ipa_smp2p_out 1>;
1270 qcom,smem-state-names = "ipa-clock-enabled-valid",
1271 "ipa-clock-enabled";
1272
1273 status = "disabled";
1274 };
1275
1276 tcsr_mutex: hwlock@1f40000 {
1277 compatible = "qcom,tcsr-mutex";
1278 reg = <0x0 0x01f40000 0x0 0x40000>;
1279 #hwlock-cells = <1>;
1280 };
1281
1282 adsp: remoteproc@3000000 {
1283 compatible = "qcom,sm6350-adsp-pas";
1284 reg = <0 0x03000000 0 0x100>;
1285
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1286 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1287 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1288 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1289 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1290 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1291 interrupt-names = "wdog", "fatal", "ready",
1292 "handover", "stop-ack";
1293
1294 clocks = <&rpmhcc RPMH_CXO_CLK>;
1295 clock-names = "xo";
1296
1297 power-domains = <&rpmhpd SM6350_LCX>,
1298 <&rpmhpd SM6350_LMX>;
1299 power-domain-names = "lcx", "lmx";
1300
1301 memory-region = <&pil_adsp_mem>;
1302
1303 qcom,qmp = <&aoss_qmp>;
1304
1305 qcom,smem-states = <&smp2p_adsp_out 0>;
1306 qcom,smem-state-names = "stop";
1307
1308 status = "disabled";
1309
1310 glink-edge {
1311 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1312 IPCC_MPROC_SIGNAL_GLINK_QMP
1313 IRQ_TYPE_EDGE_RISING>;
1314 mboxes = <&ipcc IPCC_CLIENT_LPASS
1315 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1316
1317 label = "lpass";
1318 qcom,remote-pid = <2>;
1319
1320 fastrpc {
1321 compatible = "qcom,fastrpc";
1322 qcom,glink-channels = "fastrpcglink-apps-dsp";
1323 label = "adsp";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1326
1327 compute-cb@3 {
1328 compatible = "qcom,fastrpc-compute-cb";
1329 reg = <3>;
1330 iommus = <&apps_smmu 0x1003 0x0>;
1331 };
1332
1333 compute-cb@4 {
1334 compatible = "qcom,fastrpc-compute-cb";
1335 reg = <4>;
1336 iommus = <&apps_smmu 0x1004 0x0>;
1337 };
1338
1339 compute-cb@5 {
1340 compatible = "qcom,fastrpc-compute-cb";
1341 reg = <5>;
1342 iommus = <&apps_smmu 0x1005 0x0>;
1343 qcom,nsessions = <5>;
1344 };
1345 };
1346 };
1347 };
1348
1349 gpu: gpu@3d00000 {
1350 compatible = "qcom,adreno-619.0", "qcom,adreno";
1351 reg = <0 0x03d00000 0 0x40000>,
1352 <0 0x03d9e000 0 0x1000>;
1353 reg-names = "kgsl_3d0_reg_memory",
1354 "cx_mem";
1355 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1356
1357 iommus = <&adreno_smmu 0>;
1358 operating-points-v2 = <&gpu_opp_table>;
1359 qcom,gmu = <&gmu>;
1360 nvmem-cells = <&gpu_speed_bin>;
1361 nvmem-cell-names = "speed_bin";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1362 #cooling-cells = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1363
1364 status = "disabled";
1365
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1366 gpu_zap_shader: zap-shader {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1367 memory-region = <&pil_gpu_mem>;
1368 };
1369
1370 gpu_opp_table: opp-table {
1371 compatible = "operating-points-v2";
1372
1373 opp-850000000 {
1374 opp-hz = /bits/ 64 <850000000>;
1375 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1376 opp-supported-hw = <0x02>;
1377 };
1378
1379 opp-800000000 {
1380 opp-hz = /bits/ 64 <800000000>;
1381 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1382 opp-supported-hw = <0x04>;
1383 };
1384
1385 opp-650000000 {
1386 opp-hz = /bits/ 64 <650000000>;
1387 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1388 opp-supported-hw = <0x08>;
1389 };
1390
1391 opp-565000000 {
1392 opp-hz = /bits/ 64 <565000000>;
1393 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1394 opp-supported-hw = <0x10>;
1395 };
1396
1397 opp-430000000 {
1398 opp-hz = /bits/ 64 <430000000>;
1399 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1400 opp-supported-hw = <0xff>;
1401 };
1402
1403 opp-355000000 {
1404 opp-hz = /bits/ 64 <355000000>;
1405 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1406 opp-supported-hw = <0xff>;
1407 };
1408
1409 opp-253000000 {
1410 opp-hz = /bits/ 64 <253000000>;
1411 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1412 opp-supported-hw = <0xff>;
1413 };
1414 };
1415 };
1416
1417 adreno_smmu: iommu@3d40000 {
1418 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1419 reg = <0 0x03d40000 0 0x10000>;
1420 #iommu-cells = <1>;
1421 #global-interrupts = <2>;
1422 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1432
1433 clocks = <&gpucc GPU_CC_AHB_CLK>,
1434 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1435 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1436 clock-names = "ahb",
1437 "bus",
1438 "iface";
1439
1440 power-domains = <&gpucc GPU_CX_GDSC>;
1441 };
1442
1443 gmu: gmu@3d6a000 {
1444 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1445 reg = <0 0x03d6a000 0 0x31000>,
1446 <0 0x0b290000 0 0x10000>,
1447 <0 0x0b490000 0 0x10000>;
1448 reg-names = "gmu",
1449 "gmu_pdc",
1450 "gmu_pdc_seq";
1451
1452 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1454 interrupt-names = "hfi",
1455 "gmu";
1456
1457 clocks = <&gpucc GPU_CC_AHB_CLK>,
1458 <&gpucc GPU_CC_CX_GMU_CLK>,
1459 <&gpucc GPU_CC_CXO_CLK>,
1460 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1461 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1462 clock-names = "ahb",
1463 "gmu",
1464 "cxo",
1465 "axi",
1466 "memnoc";
1467
1468 power-domains = <&gpucc GPU_CX_GDSC>,
1469 <&gpucc GPU_GX_GDSC>;
1470 power-domain-names = "cx",
1471 "gx";
1472
1473 iommus = <&adreno_smmu 5>;
1474
1475 operating-points-v2 = <&gmu_opp_table>;
1476
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1477 gmu_opp_table: opp-table {
1478 compatible = "operating-points-v2";
1479
1480 opp-200000000 {
1481 opp-hz = /bits/ 64 <200000000>;
1482 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1483 };
1484 };
1485 };
1486
1487 gpucc: clock-controller@3d90000 {
1488 compatible = "qcom,sm6350-gpucc";
1489 reg = <0 0x03d90000 0 0x9000>;
1490 clocks = <&rpmhcc RPMH_CXO_CLK>,
1491 <&gcc GCC_GPU_GPLL0_CLK>,
1492 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1493 clock-names = "bi_tcxo",
1494 "gcc_gpu_gpll0_clk_src",
1495 "gcc_gpu_gpll0_div_clk_src";
1496 #clock-cells = <1>;
1497 #reset-cells = <1>;
1498 #power-domain-cells = <1>;
1499 };
1500
1501 mpss: remoteproc@4080000 {
1502 compatible = "qcom,sm6350-mpss-pas";
1503 reg = <0x0 0x04080000 0x0 0x4040>;
1504
1505 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1506 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1507 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1508 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1509 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1510 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1511 interrupt-names = "wdog", "fatal", "ready", "handover",
1512 "stop-ack", "shutdown-ack";
1513
1514 clocks = <&rpmhcc RPMH_CXO_CLK>;
1515 clock-names = "xo";
1516
1517 power-domains = <&rpmhpd SM6350_CX>,
1518 <&rpmhpd SM6350_MSS>;
1519 power-domain-names = "cx", "mss";
1520
1521 memory-region = <&pil_modem_mem>;
1522
1523 qcom,qmp = <&aoss_qmp>;
1524
1525 qcom,smem-states = <&modem_smp2p_out 0>;
1526 qcom,smem-state-names = "stop";
1527
1528 status = "disabled";
1529
1530 glink-edge {
1531 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1532 IPCC_MPROC_SIGNAL_GLINK_QMP
1533 IRQ_TYPE_EDGE_RISING>;
1534 mboxes = <&ipcc IPCC_CLIENT_MPSS
1535 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1536 label = "modem";
1537 qcom,remote-pid = <1>;
1538 };
1539 };
1540
1541 cdsp: remoteproc@8300000 {
1542 compatible = "qcom,sm6350-cdsp-pas";
1543 reg = <0 0x08300000 0 0x10000>;
1544
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1545 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1546 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1547 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1548 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1549 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1550 interrupt-names = "wdog", "fatal", "ready",
1551 "handover", "stop-ack";
1552
1553 clocks = <&rpmhcc RPMH_CXO_CLK>;
1554 clock-names = "xo";
1555
1556 power-domains = <&rpmhpd SM6350_CX>,
1557 <&rpmhpd SM6350_MX>;
1558 power-domain-names = "cx", "mx";
1559
1560 memory-region = <&pil_cdsp_mem>;
1561
1562 qcom,qmp = <&aoss_qmp>;
1563
1564 qcom,smem-states = <&smp2p_cdsp_out 0>;
1565 qcom,smem-state-names = "stop";
1566
1567 status = "disabled";
1568
1569 glink-edge {
1570 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1571 IPCC_MPROC_SIGNAL_GLINK_QMP
1572 IRQ_TYPE_EDGE_RISING>;
1573 mboxes = <&ipcc IPCC_CLIENT_CDSP
1574 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1575
1576 label = "cdsp";
1577 qcom,remote-pid = <5>;
1578
1579 fastrpc {
1580 compatible = "qcom,fastrpc";
1581 qcom,glink-channels = "fastrpcglink-apps-dsp";
1582 label = "cdsp";
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1585
1586 compute-cb@1 {
1587 compatible = "qcom,fastrpc-compute-cb";
1588 reg = <1>;
1589 iommus = <&apps_smmu 0x1401 0x20>;
1590 };
1591
1592 compute-cb@2 {
1593 compatible = "qcom,fastrpc-compute-cb";
1594 reg = <2>;
1595 iommus = <&apps_smmu 0x1402 0x20>;
1596 };
1597
1598 compute-cb@3 {
1599 compatible = "qcom,fastrpc-compute-cb";
1600 reg = <3>;
1601 iommus = <&apps_smmu 0x1403 0x20>;
1602 };
1603
1604 compute-cb@4 {
1605 compatible = "qcom,fastrpc-compute-cb";
1606 reg = <4>;
1607 iommus = <&apps_smmu 0x1404 0x20>;
1608 };
1609
1610 compute-cb@5 {
1611 compatible = "qcom,fastrpc-compute-cb";
1612 reg = <5>;
1613 iommus = <&apps_smmu 0x1405 0x20>;
1614 };
1615
1616 compute-cb@6 {
1617 compatible = "qcom,fastrpc-compute-cb";
1618 reg = <6>;
1619 iommus = <&apps_smmu 0x1406 0x20>;
1620 };
1621
1622 compute-cb@7 {
1623 compatible = "qcom,fastrpc-compute-cb";
1624 reg = <7>;
1625 iommus = <&apps_smmu 0x1407 0x20>;
1626 };
1627
1628 compute-cb@8 {
1629 compatible = "qcom,fastrpc-compute-cb";
1630 reg = <8>;
1631 iommus = <&apps_smmu 0x1408 0x20>;
1632 };
1633
1634 /* note: secure cb9 in downstream */
1635 };
1636 };
1637 };
1638
1639 sdhc_2: mmc@8804000 {
1640 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1641 reg = <0 0x08804000 0 0x1000>;
1642
1643 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1645 interrupt-names = "hc_irq", "pwr_irq";
1646 iommus = <&apps_smmu 0x560 0x0>;
1647
1648 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1649 <&gcc GCC_SDCC2_APPS_CLK>,
1650 <&rpmhcc RPMH_CXO_CLK>;
1651 clock-names = "iface", "core", "xo";
1652 resets = <&gcc GCC_SDCC2_BCR>;
1653 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
1654 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
1655 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1656
1657 pinctrl-0 = <&sdc2_on_state>;
1658 pinctrl-1 = <&sdc2_off_state>;
1659 pinctrl-names = "default", "sleep";
1660
1661 qcom,dll-config = <0x0007642c>;
1662 qcom,ddr-config = <0x80040868>;
1663 power-domains = <&rpmhpd SM6350_CX>;
1664 operating-points-v2 = <&sdhc2_opp_table>;
1665 bus-width = <4>;
1666
1667 status = "disabled";
1668
1669 sdhc2_opp_table: opp-table {
1670 compatible = "operating-points-v2";
1671
1672 opp-100000000 {
1673 opp-hz = /bits/ 64 <100000000>;
1674 required-opps = <&rpmhpd_opp_svs_l1>;
1675 opp-peak-kBps = <790000 131000>;
1676 opp-avg-kBps = <50000 50000>;
1677 };
1678
1679 opp-202000000 {
1680 opp-hz = /bits/ 64 <202000000>;
1681 required-opps = <&rpmhpd_opp_nom>;
1682 opp-peak-kBps = <3190000 294000>;
1683 opp-avg-kBps = <261438 300000>;
1684 };
1685 };
1686 };
1687
1688 usb_1_hsphy: phy@88e3000 {
1689 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1690 reg = <0 0x088e3000 0 0x400>;
1691 status = "disabled";
1692 #phy-cells = <0>;
1693
1694 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
1695 clock-names = "cfg_ahb", "ref";
1696
1697 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1698 };
1699
1700 usb_1_qmpphy: phy@88e8000 {
1701 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1702 reg = <0 0x088e8000 0 0x3000>;
1703
1704 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1705 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1706 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1707 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1708 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1709
1710 power-domains = <&gcc USB30_PRIM_GDSC>;
1711
1712 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1713 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1714 reset-names = "phy", "common";
1715
1716 #clock-cells = <1>;
1717 #phy-cells = <1>;
1718
1719 status = "disabled";
1720 };
1721
1722 dc_noc: interconnect@9160000 {
1723 compatible = "qcom,sm6350-dc-noc";
1724 reg = <0 0x09160000 0 0x3200>;
1725 #interconnect-cells = <2>;
1726 qcom,bcm-voters = <&apps_bcm_voter>;
1727 };
1728
1729 system-cache-controller@9200000 {
1730 compatible = "qcom,sm6350-llcc";
1731 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1732 reg-names = "llcc0_base", "llcc_broadcast_base";
1733 };
1734
1735 gem_noc: interconnect@9680000 {
1736 compatible = "qcom,sm6350-gem-noc";
1737 reg = <0 0x09680000 0 0x3e200>;
1738 #interconnect-cells = <2>;
1739 qcom,bcm-voters = <&apps_bcm_voter>;
1740 };
1741
1742 npu_noc: interconnect@9990000 {
1743 compatible = "qcom,sm6350-npu-noc";
1744 reg = <0 0x09990000 0 0x1600>;
1745 #interconnect-cells = <2>;
1746 qcom,bcm-voters = <&apps_bcm_voter>;
1747 };
1748
1749 pmu@90b6300 {
1750 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1751 reg = <0x0 0x090b6300 0x0 0x600>;
1752 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
1753
1754 operating-points-v2 = <&llcc_bwmon_opp_table>;
1755 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
1756 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;
1757
1758 llcc_bwmon_opp_table: opp-table {
1759 compatible = "operating-points-v2";
1760
1761 opp-0 {
1762 opp-peak-kBps = <2288000>;
1763 };
1764
1765 opp-1 {
1766 opp-peak-kBps = <4577000>;
1767 };
1768
1769 opp-2 {
1770 opp-peak-kBps = <7110000>;
1771 };
1772
1773 opp-3 {
1774 opp-peak-kBps = <9155000>;
1775 };
1776
1777 opp-4 {
1778 opp-peak-kBps = <12298000>;
1779 };
1780
1781 opp-5 {
1782 opp-peak-kBps = <14236000>;
1783 };
1784
1785 };
1786 };
1787
1788 pmu@90cd000 {
1789 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1790 reg = <0x0 0x090cd000 0x0 0x1000>;
1791 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1792
1793 operating-points-v2 = <&cpu_bwmon_opp_table>;
1794 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
1795 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;
1796
1797 cpu_bwmon_opp_table: opp-table {
1798 compatible = "operating-points-v2";
1799
1800 opp-0 {
1801 opp-peak-kBps = <762000>;
1802 };
1803
1804 opp-1 {
1805 opp-peak-kBps = <1144000>;
1806 };
1807
1808 opp-2 {
1809 opp-peak-kBps = <1720000>;
1810 };
1811
1812 opp-3 {
1813 opp-peak-kBps = <2086000>;
1814 };
1815
1816 opp-4 {
1817 opp-peak-kBps = <2597000>;
1818 };
1819
1820 opp-5 {
1821 opp-peak-kBps = <2929000>;
1822 };
1823
1824 opp-6 {
1825 opp-peak-kBps = <3879000>;
1826 };
1827
1828 opp-7 {
1829 opp-peak-kBps = <5161000>;
1830 };
1831
1832 opp-8 {
1833 opp-peak-kBps = <5931000>;
1834 };
1835
1836 opp-9 {
1837 opp-peak-kBps = <6881000>;
1838 };
1839
1840 opp-10 {
1841 opp-peak-kBps = <7980000>;
1842 };
1843 };
1844 };
1845
1846 usb_1: usb@a6f8800 {
1847 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1848 reg = <0 0x0a6f8800 0 0x400>;
1849 status = "disabled";
1850 #address-cells = <2>;
1851 #size-cells = <2>;
1852 ranges;
1853
1854 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1855 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1856 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1857 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1858 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1859 clock-names = "cfg_noc",
1860 "core",
1861 "iface",
1862 "sleep",
1863 "mock_utmi";
1864
1865 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1866 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1867 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1868 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1869 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1870 interrupt-names = "pwr_event",
1871 "hs_phy_irq",
1872 "dp_hs_phy_irq",
1873 "dm_hs_phy_irq",
1874 "ss_phy_irq";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1875
1876 power-domains = <&gcc USB30_PRIM_GDSC>;
1877
1878 resets = <&gcc GCC_USB30_PRIM_BCR>;
1879
1880 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
1881 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1882 interconnect-names = "usb-ddr", "apps-usb";
1883
1884 usb_1_dwc3: usb@a600000 {
1885 compatible = "snps,dwc3";
1886 reg = <0 0x0a600000 0 0xcd00>;
1887 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1888 iommus = <&apps_smmu 0x540 0x0>;
1889 snps,dis_u2_susphy_quirk;
1890 snps,dis_enblslpm_quirk;
1891 snps,has-lpm-erratum;
1892 snps,hird-threshold = /bits/ 8 <0x10>;
1893 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
1894 phy-names = "usb2-phy", "usb3-phy";
1895 };
1896 };
1897
1898 cci0: cci@ac4a000 {
1899 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1900 reg = <0 0x0ac4a000 0 0x1000>;
1901 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
1902 power-domains = <&camcc TITAN_TOP_GDSC>;
1903
1904 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1905 <&camcc CAMCC_SOC_AHB_CLK>,
1906 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
1907 <&camcc CAMCC_CPAS_AHB_CLK>,
1908 <&camcc CAMCC_CCI_0_CLK>,
1909 <&camcc CAMCC_CCI_0_CLK_SRC>;
1910 clock-names = "camnoc_axi",
1911 "soc_ahb",
1912 "slow_ahb_src",
1913 "cpas_ahb",
1914 "cci",
1915 "cci_src";
1916
1917 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1918 <&camcc CAMCC_CCI_0_CLK>;
1919 assigned-clock-rates = <80000000>, <37500000>;
1920
1921 pinctrl-0 = <&cci0_default &cci1_default>;
1922 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
1923 pinctrl-names = "default", "sleep";
1924
1925 #address-cells = <1>;
1926 #size-cells = <0>;
1927
1928 status = "disabled";
1929
1930 cci0_i2c0: i2c-bus@0 {
1931 reg = <0>;
1932 clock-frequency = <1000000>;
1933 #address-cells = <1>;
1934 #size-cells = <0>;
1935 };
1936
1937 cci0_i2c1: i2c-bus@1 {
1938 reg = <1>;
1939 clock-frequency = <1000000>;
1940 #address-cells = <1>;
1941 #size-cells = <0>;
1942 };
1943 };
1944
1945 cci1: cci@ac4b000 {
1946 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1947 reg = <0 0x0ac4b000 0 0x1000>;
1948 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
1949 power-domains = <&camcc TITAN_TOP_GDSC>;
1950
1951 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1952 <&camcc CAMCC_SOC_AHB_CLK>,
1953 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
1954 <&camcc CAMCC_CPAS_AHB_CLK>,
1955 <&camcc CAMCC_CCI_1_CLK>,
1956 <&camcc CAMCC_CCI_1_CLK_SRC>;
1957 clock-names = "camnoc_axi",
1958 "soc_ahb",
1959 "slow_ahb_src",
1960 "cpas_ahb",
1961 "cci",
1962 "cci_src";
1963
1964 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1965 <&camcc CAMCC_CCI_1_CLK>;
1966 assigned-clock-rates = <80000000>, <37500000>;
1967
1968 pinctrl-0 = <&cci2_default>;
1969 pinctrl-1 = <&cci2_sleep>;
1970 pinctrl-names = "default", "sleep";
1971
1972 #address-cells = <1>;
1973 #size-cells = <0>;
1974
1975 status = "disabled";
1976
1977 cci1_i2c0: i2c-bus@0 {
1978 reg = <0>;
1979 clock-frequency = <1000000>;
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1982 };
1983
1984 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */
1985 };
1986
1987 camcc: clock-controller@ad00000 {
1988 compatible = "qcom,sm6350-camcc";
1989 reg = <0 0x0ad00000 0 0x16000>;
1990 clocks = <&rpmhcc RPMH_CXO_CLK>;
1991 #clock-cells = <1>;
1992 #reset-cells = <1>;
1993 #power-domain-cells = <1>;
1994 };
1995
1996 mdss: display-subsystem@ae00000 {
1997 compatible = "qcom,sm6350-mdss";
1998 reg = <0 0x0ae00000 0 0x1000>;
1999 reg-names = "mdss";
2000
2001 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2002 interrupt-controller;
2003 #interrupt-cells = <1>;
2004
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2005 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
2006 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2007 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
2008 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2009 interconnect-names = "mdp0-mem",
2010 "cpu-cfg";
2011
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2012 clocks = <&gcc GCC_DISP_AHB_CLK>,
2013 <&gcc GCC_DISP_AXI_CLK>,
2014 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2015 clock-names = "iface",
2016 "bus",
2017 "core";
2018
2019 power-domains = <&dispcc MDSS_GDSC>;
2020 iommus = <&apps_smmu 0x800 0x2>;
2021
2022 #address-cells = <2>;
2023 #size-cells = <2>;
2024 ranges;
2025
2026 status = "disabled";
2027
2028 mdss_mdp: display-controller@ae01000 {
2029 compatible = "qcom,sm6350-dpu";
2030 reg = <0 0x0ae01000 0 0x8f000>,
2031 <0 0x0aeb0000 0 0x2008>;
2032 reg-names = "mdp", "vbif";
2033
2034 interrupt-parent = <&mdss>;
2035 interrupts = <0>;
2036
2037 clocks = <&gcc GCC_DISP_AXI_CLK>,
2038 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2039 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2040 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2041 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2042 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2043 clock-names = "bus",
2044 "iface",
2045 "rot",
2046 "lut",
2047 "core",
2048 "vsync";
2049
2050 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2051 assigned-clock-rates = <19200000>;
2052
2053 operating-points-v2 = <&mdp_opp_table>;
2054 power-domains = <&rpmhpd SM6350_CX>;
2055
2056 ports {
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2059
2060 port@0 {
2061 reg = <0>;
2062
2063 dpu_intf1_out: endpoint {
2064 remote-endpoint = <&mdss_dsi0_in>;
2065 };
2066 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]2067
2068 port@2 {
2069 reg = <2>;
2070
2071 dpu_intf0_out: endpoint {
2072 remote-endpoint = <&mdss_dp_in>;
2073 };
2074 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2075 };
2076
2077 mdp_opp_table: opp-table {
2078 compatible = "operating-points-v2";
2079
2080 opp-19200000 {
2081 opp-hz = /bits/ 64 <19200000>;
2082 required-opps = <&rpmhpd_opp_min_svs>;
2083 };
2084
2085 opp-200000000 {
2086 opp-hz = /bits/ 64 <200000000>;
2087 required-opps = <&rpmhpd_opp_low_svs>;
2088 };
2089
2090 opp-300000000 {
2091 opp-hz = /bits/ 64 <300000000>;
2092 required-opps = <&rpmhpd_opp_svs>;
2093 };
2094
2095 opp-373333333 {
2096 opp-hz = /bits/ 64 <373333333>;
2097 required-opps = <&rpmhpd_opp_svs_l1>;
2098 };
2099
2100 opp-448000000 {
2101 opp-hz = /bits/ 64 <448000000>;
2102 required-opps = <&rpmhpd_opp_nom>;
2103 };
2104
2105 opp-560000000 {
2106 opp-hz = /bits/ 64 <560000000>;
2107 required-opps = <&rpmhpd_opp_turbo>;
2108 };
2109 };
2110 };
2111
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]2112 mdss_dp: displayport-controller@ae90000 {
2113 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
2114 reg = <0 0xae90000 0 0x200>,
2115 <0 0xae90200 0 0x200>,
2116 <0 0xae90400 0 0x600>,
2117 <0 0xae91000 0 0x400>,
2118 <0 0xae91400 0 0x400>;
2119 interrupt-parent = <&mdss>;
2120 interrupts = <12>;
2121 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2122 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2123 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2124 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2125 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2126 clock-names = "core_iface",
2127 "core_aux",
2128 "ctrl_link",
2129 "ctrl_link_iface",
2130 "stream_pixel";
2131
2132 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2133 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2134 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2135 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2136
2137 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2138 phy-names = "dp";
2139
2140 #sound-dai-cells = <0>;
2141
2142 operating-points-v2 = <&dp_opp_table>;
2143 power-domains = <&rpmhpd SM6350_CX>;
2144
2145 status = "disabled";
2146
2147 ports {
2148 #address-cells = <1>;
2149 #size-cells = <0>;
2150
2151 port@0 {
2152 reg = <0>;
2153
2154 mdss_dp_in: endpoint {
2155 remote-endpoint = <&dpu_intf0_out>;
2156 };
2157 };
2158
2159 port@1 {
2160 reg = <1>;
2161
2162 mdss_dp_out: endpoint {
2163 };
2164 };
2165 };
2166
2167 dp_opp_table: opp-table {
2168 compatible = "operating-points-v2";
2169
2170 opp-160000000 {
2171 opp-hz = /bits/ 64 <160000000>;
2172 required-opps = <&rpmhpd_opp_low_svs>;
2173 };
2174
2175 opp-270000000 {
2176 opp-hz = /bits/ 64 <270000000>;
2177 required-opps = <&rpmhpd_opp_svs>;
2178 };
2179
2180 opp-540000000 {
2181 opp-hz = /bits/ 64 <540000000>;
2182 required-opps = <&rpmhpd_opp_svs_l1>;
2183 };
2184
2185 opp-810000000 {
2186 opp-hz = /bits/ 64 <810000000>;
2187 required-opps = <&rpmhpd_opp_nom>;
2188 };
2189 };
2190 };
2191
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2192 mdss_dsi0: dsi@ae94000 {
2193 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2194 reg = <0 0x0ae94000 0 0x400>;
2195 reg-names = "dsi_ctrl";
2196
2197 interrupt-parent = <&mdss>;
2198 interrupts = <4>;
2199
2200 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2201 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2202 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2203 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2204 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2205 <&gcc GCC_DISP_AXI_CLK>;
2206 clock-names = "byte",
2207 "byte_intf",
2208 "pixel",
2209 "core",
2210 "iface",
2211 "bus";
2212
2213 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2214 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2215 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2216
2217 operating-points-v2 = <&mdss_dsi_opp_table>;
2218 power-domains = <&rpmhpd SM6350_MX>;
2219
2220 phys = <&mdss_dsi0_phy>;
2221 phy-names = "dsi";
2222
2223 #address-cells = <1>;
2224 #size-cells = <0>;
2225
2226 status = "disabled";
2227
2228 ports {
2229 #address-cells = <1>;
2230 #size-cells = <0>;
2231
2232 port@0 {
2233 reg = <0>;
2234
2235 mdss_dsi0_in: endpoint {
2236 remote-endpoint = <&dpu_intf1_out>;
2237 };
2238 };
2239
2240 port@1 {
2241 reg = <1>;
2242
2243 mdss_dsi0_out: endpoint {
2244 };
2245 };
2246 };
2247
2248 mdss_dsi_opp_table: opp-table {
2249 compatible = "operating-points-v2";
2250
2251 opp-187500000 {
2252 opp-hz = /bits/ 64 <187500000>;
2253 required-opps = <&rpmhpd_opp_low_svs>;
2254 };
2255
2256 opp-300000000 {
2257 opp-hz = /bits/ 64 <300000000>;
2258 required-opps = <&rpmhpd_opp_svs>;
2259 };
2260
2261 opp-358000000 {
2262 opp-hz = /bits/ 64 <358000000>;
2263 required-opps = <&rpmhpd_opp_svs_l1>;
2264 };
2265 };
2266 };
2267
2268 mdss_dsi0_phy: phy@ae94400 {
2269 compatible = "qcom,dsi-phy-10nm";
2270 reg = <0 0x0ae94400 0 0x200>,
2271 <0 0x0ae94600 0 0x280>,
2272 <0 0x0ae94a00 0 0x1e0>;
2273 reg-names = "dsi_phy",
2274 "dsi_phy_lane",
2275 "dsi_pll";
2276
2277 #clock-cells = <1>;
2278 #phy-cells = <0>;
2279
2280 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2281 <&rpmhcc RPMH_CXO_CLK>;
2282 clock-names = "iface", "ref";
2283
2284 status = "disabled";
2285 };
2286 };
2287
2288 dispcc: clock-controller@af00000 {
2289 compatible = "qcom,sm6350-dispcc";
2290 reg = <0 0x0af00000 0 0x20000>;
2291 clocks = <&rpmhcc RPMH_CXO_CLK>,
2292 <&gcc GCC_DISP_GPLL0_CLK>,
2293 <&mdss_dsi0_phy 0>,
2294 <&mdss_dsi0_phy 1>,
2295 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2296 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2297 clock-names = "bi_tcxo",
2298 "gcc_disp_gpll0_clk",
2299 "dsi0_phy_pll_out_byteclk",
2300 "dsi0_phy_pll_out_dsiclk",
2301 "dp_phy_pll_link_clk",
2302 "dp_phy_pll_vco_div_clk";
2303 #clock-cells = <1>;
2304 #reset-cells = <1>;
2305 #power-domain-cells = <1>;
2306 };
2307
2308 pdc: interrupt-controller@b220000 {
2309 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2310 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
2311 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2312 <125 63 1>, <126 655 12>, <138 139 15>;
2313 #interrupt-cells = <2>;
2314 interrupt-parent = <&intc>;
2315 interrupt-controller;
2316 };
2317
2318 tsens0: thermal-sensor@c263000 {
2319 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2320 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2321 <0 0x0c222000 0 0x8>; /* SROT */
2322 #qcom,sensors = <16>;
2323 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2324 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2325 interrupt-names = "uplow", "critical";
2326 #thermal-sensor-cells = <1>;
2327 };
2328
2329 tsens1: thermal-sensor@c265000 {
2330 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2331 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2332 <0 0x0c223000 0 0x8>; /* SROT */
2333 #qcom,sensors = <16>;
2334 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2335 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2336 interrupt-names = "uplow", "critical";
2337 #thermal-sensor-cells = <1>;
2338 };
2339
2340 aoss_qmp: power-management@c300000 {
2341 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2342 reg = <0 0x0c300000 0 0x1000>;
2343 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2344 IRQ_TYPE_EDGE_RISING>;
2345 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2346
2347 #clock-cells = <0>;
2348 };
2349
2350 spmi_bus: spmi@c440000 {
2351 compatible = "qcom,spmi-pmic-arb";
2352 reg = <0 0x0c440000 0 0x1100>,
2353 <0 0x0c600000 0 0x2000000>,
2354 <0 0x0e600000 0 0x100000>,
2355 <0 0x0e700000 0 0xa0000>,
2356 <0 0x0c40a000 0 0x26000>;
2357 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2358 interrupt-names = "periph_irq";
2359 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2360 qcom,ee = <0>;
2361 qcom,channel = <0>;
2362 #address-cells = <2>;
2363 #size-cells = <0>;
2364 interrupt-controller;
2365 #interrupt-cells = <4>;
2366 };
2367
2368 tlmm: pinctrl@f100000 {
2369 compatible = "qcom,sm6350-tlmm";
2370 reg = <0 0x0f100000 0 0x300000>;
2371 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
2374 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
2375 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
2376 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
2377 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
2378 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
2379 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
2380 gpio-controller;
2381 #gpio-cells = <2>;
2382 interrupt-controller;
2383 #interrupt-cells = <2>;
2384 gpio-ranges = <&tlmm 0 0 157>;
2385 wakeup-parent = <&pdc>;
2386
2387 cci0_default: cci0-default-state {
2388 pins = "gpio39", "gpio40";
2389 function = "cci_i2c";
2390 drive-strength = <2>;
2391 bias-pull-up;
2392 };
2393
2394 cci0_sleep: cci0-sleep-state {
2395 pins = "gpio39", "gpio40";
2396 function = "cci_i2c";
2397 drive-strength = <2>;
2398 bias-pull-down;
2399 };
2400
2401 cci1_default: cci1-default-state {
2402 pins = "gpio41", "gpio42";
2403 function = "cci_i2c";
2404 drive-strength = <2>;
2405 bias-pull-up;
2406 };
2407
2408 cci1_sleep: cci1-sleep-state {
2409 pins = "gpio41", "gpio42";
2410 function = "cci_i2c";
2411 drive-strength = <2>;
2412 bias-pull-down;
2413 };
2414
2415 cci2_default: cci2-default-state {
2416 pins = "gpio43", "gpio44";
2417 function = "cci_i2c";
2418 drive-strength = <2>;
2419 bias-pull-up;
2420 };
2421
2422 cci2_sleep: cci2-sleep-state {
2423 pins = "gpio43", "gpio44";
2424 function = "cci_i2c";
2425 drive-strength = <2>;
2426 bias-pull-down;
2427 };
2428
2429 sdc2_off_state: sdc2-off-state {
2430 clk-pins {
2431 pins = "sdc2_clk";
2432 drive-strength = <2>;
2433 bias-disable;
2434 };
2435
2436 cmd-pins {
2437 pins = "sdc2_cmd";
2438 drive-strength = <2>;
2439 bias-pull-up;
2440 };
2441
2442 data-pins {
2443 pins = "sdc2_data";
2444 drive-strength = <2>;
2445 bias-pull-up;
2446 };
2447 };
2448
2449 sdc2_on_state: sdc2-on-state {
2450 clk-pins {
2451 pins = "sdc2_clk";
2452 drive-strength = <16>;
2453 bias-disable;
2454 };
2455
2456 cmd-pins {
2457 pins = "sdc2_cmd";
2458 drive-strength = <10>;
2459 bias-pull-up;
2460 };
2461
2462 data-pins {
2463 pins = "sdc2_data";
2464 drive-strength = <10>;
2465 bias-pull-up;
2466 };
2467 };
2468
2469 qup_uart9_default: qup-uart9-default-state {
2470 pins = "gpio25", "gpio26";
2471 function = "qup13_f2";
2472 drive-strength = <2>;
2473 bias-disable;
2474 };
2475
2476 qup_i2c0_default: qup-i2c0-default-state {
2477 pins = "gpio0", "gpio1";
2478 function = "qup00";
2479 drive-strength = <2>;
2480 bias-pull-up;
2481 };
2482
2483 qup_i2c2_default: qup-i2c2-default-state {
2484 pins = "gpio45", "gpio46";
2485 function = "qup02";
2486 drive-strength = <2>;
2487 bias-pull-up;
2488 };
2489
2490 qup_i2c6_default: qup-i2c6-default-state {
2491 pins = "gpio13", "gpio14";
2492 function = "qup10";
2493 drive-strength = <2>;
2494 bias-pull-up;
2495 };
2496
2497 qup_i2c7_default: qup-i2c7-default-state {
2498 pins = "gpio27", "gpio28";
2499 function = "qup11";
2500 drive-strength = <2>;
2501 bias-pull-up;
2502 };
2503
2504 qup_i2c8_default: qup-i2c8-default-state {
2505 pins = "gpio19", "gpio20";
2506 function = "qup12";
2507 drive-strength = <2>;
2508 bias-pull-up;
2509 };
2510
2511 qup_i2c10_default: qup-i2c10-default-state {
2512 pins = "gpio4", "gpio5";
2513 function = "qup14";
2514 drive-strength = <2>;
2515 bias-pull-up;
2516 };
2517
2518 qup_uart1_cts: qup-uart1-cts-default-state {
2519 pins = "gpio61";
2520 function = "qup01";
2521 drive-strength = <2>;
2522 bias-disable;
2523 };
2524
2525 qup_uart1_rts: qup-uart1-rts-default-state {
2526 pins = "gpio62";
2527 function = "qup01";
2528 drive-strength = <2>;
2529 bias-pull-down;
2530 };
2531
2532 qup_uart1_rx: qup-uart1-rx-default-state {
2533 pins = "gpio64";
2534 function = "qup01";
2535 drive-strength = <2>;
2536 bias-disable;
2537 };
2538
2539 qup_uart1_tx: qup-uart1-tx-default-state {
2540 pins = "gpio63";
2541 function = "qup01";
2542 drive-strength = <2>;
2543 bias-pull-up;
2544 };
2545 };
2546
2547 apps_smmu: iommu@15000000 {
2548 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2549 reg = <0 0x15000000 0 0x100000>;
2550 #iommu-cells = <2>;
2551 #global-interrupts = <1>;
2552 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2553 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2554 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2555 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2556 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2557 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2558 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2559 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2560 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2561 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2562 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2563 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2564 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2565 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2566 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2567 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2568 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2569 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2570 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2571 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2572 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2573 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2574 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2575 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2578 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2579 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2580 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2581 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2583 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2584 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2585 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2586 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2587 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2588 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2589 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2590 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2591 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2592 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2593 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2594 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2595 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2596 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2597 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2598 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2599 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2600 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2601 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2602 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2603 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2604 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2607 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2608 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2609 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2610 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2611 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2612 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2613 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2614 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2615 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2616 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2617 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2618 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2619 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2620 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2621 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2622 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2623 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2624 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2625 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2626 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2627 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2628 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2629 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2630 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2631 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2632 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
2633 };
2634
2635 intc: interrupt-controller@17a00000 {
2636 compatible = "arm,gic-v3";
2637 #interrupt-cells = <3>;
2638 interrupt-controller;
2639 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2640 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2641 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
2642 };
2643
2644 watchdog@17c10000 {
2645 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2646 reg = <0 0x17c10000 0 0x1000>;
2647 clocks = <&sleep_clk>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2648 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2649 };
2650
2651 timer@17c20000 {
2652 compatible = "arm,armv7-timer-mem";
2653 reg = <0x0 0x17c20000 0x0 0x1000>;
2654 clock-frequency = <19200000>;
2655 #address-cells = <1>;
2656 #size-cells = <1>;
2657 ranges = <0 0 0 0x20000000>;
2658
2659 frame@17c21000 {
2660 frame-number = <0>;
2661 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2662 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2663 reg = <0x17c21000 0x1000>,
2664 <0x17c22000 0x1000>;
2665 };
2666
2667 frame@17c23000 {
2668 frame-number = <1>;
2669 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2670 reg = <0x17c23000 0x1000>;
2671 status = "disabled";
2672 };
2673
2674 frame@17c25000 {
2675 frame-number = <2>;
2676 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2677 reg = <0x17c25000 0x1000>;
2678 status = "disabled";
2679 };
2680
2681 frame@17c27000 {
2682 frame-number = <3>;
2683 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2684 reg = <0x17c27000 0x1000>;
2685 status = "disabled";
2686 };
2687
2688 frame@17c29000 {
2689 frame-number = <4>;
2690 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2691 reg = <0x17c29000 0x1000>;
2692 status = "disabled";
2693 };
2694
2695 frame@17c2b000 {
2696 frame-number = <5>;
2697 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2698 reg = <0x17c2b000 0x1000>;
2699 status = "disabled";
2700 };
2701
2702 frame@17c2d000 {
2703 frame-number = <6>;
2704 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2705 reg = <0x17c2d000 0x1000>;
2706 status = "disabled";
2707 };
2708 };
2709
2710 apps_rsc: rsc@18200000 {
2711 compatible = "qcom,rpmh-rsc";
2712 label = "apps_rsc";
2713 reg = <0x0 0x18200000 0x0 0x10000>,
2714 <0x0 0x18210000 0x0 0x10000>,
2715 <0x0 0x18220000 0x0 0x10000>;
2716 reg-names = "drv-0", "drv-1", "drv-2";
2717 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2718 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2719 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2720 qcom,tcs-offset = <0xd00>;
2721 qcom,drv-id = <2>;
2722 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2723 <WAKE_TCS 3>, <CONTROL_TCS 1>;
2724 power-domains = <&CLUSTER_PD>;
2725
2726 rpmhcc: clock-controller {
2727 compatible = "qcom,sm6350-rpmh-clk";
2728 #clock-cells = <1>;
2729 clock-names = "xo";
2730 clocks = <&xo_board>;
2731 };
2732
2733 rpmhpd: power-controller {
2734 compatible = "qcom,sm6350-rpmhpd";
2735 #power-domain-cells = <1>;
2736 operating-points-v2 = <&rpmhpd_opp_table>;
2737
2738 rpmhpd_opp_table: opp-table {
2739 compatible = "operating-points-v2";
2740
2741 rpmhpd_opp_ret: opp1 {
2742 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2743 };
2744
2745 rpmhpd_opp_min_svs: opp2 {
2746 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2747 };
2748
2749 rpmhpd_opp_low_svs: opp3 {
2750 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2751 };
2752
2753 rpmhpd_opp_svs: opp4 {
2754 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2755 };
2756
2757 rpmhpd_opp_svs_l1: opp5 {
2758 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2759 };
2760
2761 rpmhpd_opp_nom: opp6 {
2762 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2763 };
2764
2765 rpmhpd_opp_nom_l1: opp7 {
2766 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2767 };
2768
2769 rpmhpd_opp_nom_l2: opp8 {
2770 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2771 };
2772
2773 rpmhpd_opp_turbo: opp9 {
2774 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2775 };
2776
2777 rpmhpd_opp_turbo_l1: opp10 {
2778 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2779 };
2780 };
2781 };
2782
2783 apps_bcm_voter: bcm-voter {
2784 compatible = "qcom,bcm-voter";
2785 };
2786 };
2787
2788 osm_l3: interconnect@18321000 {
2789 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2790 reg = <0x0 0x18321000 0x0 0x1000>;
2791
2792 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2793 clock-names = "xo", "alternate";
2794
2795 #interconnect-cells = <1>;
2796 };
2797
2798 cpufreq_hw: cpufreq@18323000 {
2799 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2800 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
2801 reg-names = "freq-domain0", "freq-domain1";
2802 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2803 clock-names = "xo", "alternate";
2804
2805 #freq-domain-cells = <1>;
2806 #clock-cells = <1>;
2807 };
2808
2809 wifi: wifi@18800000 {
2810 compatible = "qcom,wcn3990-wifi";
2811 reg = <0 0x18800000 0 0x800000>;
2812 reg-names = "membase";
2813 memory-region = <&wlan_fw_mem>;
2814 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2815 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2816 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2817 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2818 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2819 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2820 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2821 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2822 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2823 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2824 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2825 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2826 iommus = <&apps_smmu 0x20 0x1>;
2827 qcom,msa-fixed-perm;
2828 status = "disabled";
2829 };
2830 };
2831
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2832 thermal-zones {
2833 aoss0-thermal {
2834 polling-delay-passive = <0>;
2835 polling-delay = <0>;
2836
2837 thermal-sensors = <&tsens0 0>;
2838
2839 trips {
2840 aoss0-crit {
2841 temperature = <125000>;
2842 hysteresis = <0>;
2843 type = "critical";
2844 };
2845 };
2846 };
2847
2848 aoss1-thermal {
2849 polling-delay-passive = <0>;
2850 polling-delay = <0>;
2851
2852 thermal-sensors = <&tsens1 0>;
2853
2854 trips {
2855 aoss1-crit {
2856 temperature = <125000>;
2857 hysteresis = <0>;
2858 type = "critical";
2859 };
2860 };
2861 };
2862
2863 audio-thermal {
2864 polling-delay-passive = <0>;
2865 polling-delay = <0>;
2866
2867 thermal-sensors = <&tsens1 2>;
2868
2869 trips {
2870 audio-crit {
2871 temperature = <125000>;
2872 hysteresis = <0>;
2873 type = "critical";
2874 };
2875 };
2876 };
2877
2878 camera-thermal {
2879 polling-delay-passive = <0>;
2880 polling-delay = <0>;
2881
2882 thermal-sensors = <&tsens1 5>;
2883
2884 trips {
2885 camera-crit {
2886 temperature = <125000>;
2887 hysteresis = <0>;
2888 type = "critical";
2889 };
2890 };
2891 };
2892
2893 cpu0-thermal {
2894 polling-delay-passive = <0>;
2895 polling-delay = <0>;
2896
2897 thermal-sensors = <&tsens0 1>;
2898
2899 trips {
2900 cpu0_alert0: trip-point0 {
2901 temperature = <95000>;
2902 hysteresis = <2000>;
2903 type = "passive";
2904 };
2905
2906 cpu0-crit {
2907 temperature = <115000>;
2908 hysteresis = <0>;
2909 type = "critical";
2910 };
2911 };
2912
2913 cooling-maps {
2914 map0 {
2915 trip = <&cpu0_alert0>;
2916 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2917 };
2918 };
2919 };
2920
2921 cpu1-thermal {
2922 polling-delay-passive = <0>;
2923 polling-delay = <0>;
2924
2925 thermal-sensors = <&tsens0 2>;
2926
2927 trips {
2928 cpu1_alert0: trip-point0 {
2929 temperature = <95000>;
2930 hysteresis = <2000>;
2931 type = "passive";
2932 };
2933
2934 cpu1-crit {
2935 temperature = <115000>;
2936 hysteresis = <0>;
2937 type = "critical";
2938 };
2939 };
2940
2941 cooling-maps {
2942 map0 {
2943 trip = <&cpu1_alert0>;
2944 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2945 };
2946 };
2947 };
2948
2949 cpu2-thermal {
2950 polling-delay-passive = <0>;
2951 polling-delay = <0>;
2952
2953 thermal-sensors = <&tsens0 3>;
2954
2955 trips {
2956 cpu2_alert0: trip-point0 {
2957 temperature = <95000>;
2958 hysteresis = <2000>;
2959 type = "passive";
2960 };
2961
2962 cpu2-crit {
2963 temperature = <115000>;
2964 hysteresis = <0>;
2965 type = "critical";
2966 };
2967 };
2968
2969 cooling-maps {
2970 map0 {
2971 trip = <&cpu2_alert0>;
2972 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2973 };
2974 };
2975 };
2976
2977 cpu3-thermal {
2978 polling-delay-passive = <0>;
2979 polling-delay = <0>;
2980
2981 thermal-sensors = <&tsens0 4>;
2982
2983 trips {
2984 cpu3_alert0: trip-point0 {
2985 temperature = <95000>;
2986 hysteresis = <2000>;
2987 type = "passive";
2988 };
2989
2990 cpu3-crit {
2991 temperature = <115000>;
2992 hysteresis = <0>;
2993 type = "critical";
2994 };
2995 };
2996
2997 cooling-maps {
2998 map0 {
2999 trip = <&cpu3_alert0>;
3000 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3001 };
3002 };
3003 };
3004
3005 cpu4-thermal {
3006 polling-delay-passive = <0>;
3007 polling-delay = <0>;
3008
3009 thermal-sensors = <&tsens0 5>;
3010
3011 trips {
3012 cpu4_alert0: trip-point0 {
3013 temperature = <95000>;
3014 hysteresis = <2000>;
3015 type = "passive";
3016 };
3017
3018 cpu4-crit {
3019 temperature = <115000>;
3020 hysteresis = <0>;
3021 type = "critical";
3022 };
3023 };
3024
3025 cooling-maps {
3026 map0 {
3027 trip = <&cpu4_alert0>;
3028 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3029 };
3030 };
3031 };
3032
3033 cpu5-thermal {
3034 polling-delay-passive = <0>;
3035 polling-delay = <0>;
3036
3037 thermal-sensors = <&tsens0 6>;
3038
3039 trips {
3040 cpu5_alert0: trip-point0 {
3041 temperature = <95000>;
3042 hysteresis = <2000>;
3043 type = "passive";
3044 };
3045
3046 cpu5-crit {
3047 temperature = <115000>;
3048 hysteresis = <0>;
3049 type = "critical";
3050 };
3051 };
3052
3053 cooling-maps {
3054 map0 {
3055 trip = <&cpu5_alert0>;
3056 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3057 };
3058 };
3059 };
3060
3061 cpu6-left-thermal {
3062 polling-delay-passive = <0>;
3063 polling-delay = <0>;
3064
3065 thermal-sensors = <&tsens0 9>;
3066
3067 trips {
3068 cpu6_left_alert0: trip-point0 {
3069 temperature = <95000>;
3070 hysteresis = <2000>;
3071 type = "passive";
3072 };
3073
3074 cpu6-left-crit {
3075 temperature = <115000>;
3076 hysteresis = <0>;
3077 type = "critical";
3078 };
3079 };
3080
3081 cooling-maps {
3082 map0 {
3083 trip = <&cpu6_left_alert0>;
3084 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3085 };
3086 };
3087 };
3088
3089 cpu6-right-thermal {
3090 polling-delay-passive = <0>;
3091 polling-delay = <0>;
3092
3093 thermal-sensors = <&tsens0 10>;
3094
3095 trips {
3096 cpu6_right_alert0: trip-point0 {
3097 temperature = <95000>;
3098 hysteresis = <2000>;
3099 type = "passive";
3100 };
3101
3102 cpu6-right-crit {
3103 temperature = <115000>;
3104 hysteresis = <0>;
3105 type = "critical";
3106 };
3107 };
3108
3109 cooling-maps {
3110 map0 {
3111 trip = <&cpu6_right_alert0>;
3112 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3113 };
3114 };
3115 };
3116
3117 cpu7-left-thermal {
3118 polling-delay-passive = <0>;
3119 polling-delay = <0>;
3120
3121 thermal-sensors = <&tsens0 11>;
3122
3123 trips {
3124 cpu7_left_alert0: trip-point0 {
3125 temperature = <95000>;
3126 hysteresis = <2000>;
3127 type = "passive";
3128 };
3129
3130 cpu7-left-crit {
3131 temperature = <115000>;
3132 hysteresis = <0>;
3133 type = "critical";
3134 };
3135 };
3136
3137 cooling-maps {
3138 map0 {
3139 trip = <&cpu7_left_alert0>;
3140 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3141 };
3142 };
3143 };
3144
3145 cpu7-right-thermal {
3146 polling-delay-passive = <0>;
3147 polling-delay = <0>;
3148
3149 thermal-sensors = <&tsens0 12>;
3150
3151 trips {
3152 cpu7_right_alert0: trip-point0 {
3153 temperature = <95000>;
3154 hysteresis = <2000>;
3155 type = "passive";
3156 };
3157
3158 cpu7-right-crit {
3159 temperature = <115000>;
3160 hysteresis = <0>;
3161 type = "critical";
3162 };
3163 };
3164
3165 cooling-maps {
3166 map0 {
3167 trip = <&cpu7_right_alert0>;
3168 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3169 };
3170 };
3171 };
3172
3173 cpuss0-thermal {
3174 polling-delay-passive = <0>;
3175 polling-delay = <0>;
3176
3177 thermal-sensors = <&tsens0 7>;
3178
3179 trips {
3180 cpuss0-crit {
3181 temperature = <125000>;
3182 hysteresis = <0>;
3183 type = "critical";
3184 };
3185 };
3186 };
3187
3188 cpuss1-thermal {
3189 polling-delay-passive = <0>;
3190 polling-delay = <0>;
3191
3192 thermal-sensors = <&tsens0 8>;
3193
3194 trips {
3195 cpuss1-crit {
3196 temperature = <125000>;
3197 hysteresis = <0>;
3198 type = "critical";
3199 };
3200 };
3201 };
3202
3203 cwlan-thermal {
3204 polling-delay-passive = <0>;
3205 polling-delay = <0>;
3206
3207 thermal-sensors = <&tsens1 1>;
3208
3209 trips {
3210 cwlan-crit {
3211 temperature = <125000>;
3212 hysteresis = <0>;
3213 type = "critical";
3214 };
3215 };
3216 };
3217
3218 ddr-thermal {
3219 polling-delay-passive = <0>;
3220 polling-delay = <0>;
3221
3222 thermal-sensors = <&tsens1 3>;
3223
3224 trips {
3225 ddr-crit {
3226 temperature = <125000>;
3227 hysteresis = <0>;
3228 type = "critical";
3229 };
3230 };
3231 };
3232
3233 gpuss0-thermal {
3234 polling-delay-passive = <0>;
3235 polling-delay = <0>;
3236
3237 thermal-sensors = <&tsens0 13>;
3238
3239 trips {
3240 gpuss0_alert0: trip-point0 {
3241 temperature = <95000>;
3242 hysteresis = <2000>;
3243 type = "passive";
3244 };
3245
3246 gpuss0-crit {
3247 temperature = <115000>;
3248 hysteresis = <0>;
3249 type = "critical";
3250 };
3251 };
3252
3253 cooling-maps {
3254 map0 {
3255 trip = <&gpuss0_alert0>;
3256 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3257 };
3258 };
3259 };
3260
3261 gpuss1-thermal {
3262 polling-delay-passive = <0>;
3263 polling-delay = <0>;
3264
3265 thermal-sensors = <&tsens0 14>;
3266
3267 trips {
3268 gpuss1_alert0: trip-point0 {
3269 temperature = <95000>;
3270 hysteresis = <2000>;
3271 type = "passive";
3272 };
3273
3274 gpuss1-crit {
3275 temperature = <115000>;
3276 hysteresis = <0>;
3277 type = "critical";
3278 };
3279 };
3280
3281 cooling-maps {
3282 map0 {
3283 trip = <&gpuss1_alert0>;
3284 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3285 };
3286 };
3287 };
3288
3289 modem-core0-thermal {
3290 polling-delay-passive = <0>;
3291 polling-delay = <0>;
3292
3293 thermal-sensors = <&tsens1 6>;
3294
3295 trips {
3296 modem-core0-crit {
3297 temperature = <125000>;
3298 hysteresis = <0>;
3299 type = "critical";
3300 };
3301 };
3302 };
3303
3304 modem-core1-thermal {
3305 polling-delay-passive = <0>;
3306 polling-delay = <0>;
3307
3308 thermal-sensors = <&tsens1 7>;
3309
3310 trips {
3311 modem-core1-crit {
3312 temperature = <125000>;
3313 hysteresis = <0>;
3314 type = "critical";
3315 };
3316 };
3317 };
3318
3319 modem-scl-thermal {
3320 polling-delay-passive = <0>;
3321 polling-delay = <0>;
3322
3323 thermal-sensors = <&tsens1 9>;
3324
3325 trips {
3326 modem-scl-crit {
3327 temperature = <125000>;
3328 hysteresis = <0>;
3329 type = "critical";
3330 };
3331 };
3332 };
3333
3334 modem-vec-thermal {
3335 polling-delay-passive = <0>;
3336 polling-delay = <0>;
3337
3338 thermal-sensors = <&tsens1 8>;
3339
3340 trips {
3341 modem-vec-crit {
3342 temperature = <125000>;
3343 hysteresis = <0>;
3344 type = "critical";
3345 };
3346 };
3347 };
3348
3349 npu-thermal {
3350 polling-delay-passive = <0>;
3351 polling-delay = <0>;
3352
3353 thermal-sensors = <&tsens1 10>;
3354
3355 trips {
3356 npu-crit {
3357 temperature = <125000>;
3358 hysteresis = <0>;
3359 type = "critical";
3360 };
3361 };
3362 };
3363
3364 q6-hvx-thermal {
3365 polling-delay-passive = <0>;
3366 polling-delay = <0>;
3367
3368 thermal-sensors = <&tsens1 4>;
3369
3370 trips {
3371 q6-hvx-crit {
3372 temperature = <125000>;
3373 hysteresis = <0>;
3374 type = "critical";
3375 };
3376 };
3377 };
3378
3379 video-thermal {
3380 polling-delay-passive = <0>;
3381 polling-delay = <0>;
3382
3383 thermal-sensors = <&tsens1 11>;
3384
3385 trips {
3386 video-crit {
3387 temperature = <125000>;
3388 hysteresis = <0>;
3389 type = "critical";
3390 };
3391 };
3392 };
3393 };
3394
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3395 timer {
3396 compatible = "arm,armv8-timer";
3397 clock-frequency = <19200000>;
3398 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3399 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3400 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3401 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3402 };
3403};