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Jianchao Wange5332ba2019-07-19 00:30:01 +03001/* SPDX-License-Identifier: GPL-2.0
Vladimir Oltean5041e422021-09-17 14:27:13 +03002 * Copyright 2016-2019 NXP
Jianchao Wange5332ba2019-07-19 00:30:01 +03003 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
4 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
9#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
10
Jianchao Wange5332ba2019-07-19 00:30:01 +030011#define CONFIG_DEEP_SLEEP
12
Jianchao Wange5332ba2019-07-19 00:30:01 +030013#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
14#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
15
16/* XHCI Support - enabled by default */
17#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
18
Jianchao Wange5332ba2019-07-19 00:30:01 +030019#define DDR_SDRAM_CFG 0x470c0008
20#define DDR_CS0_BNDS 0x008000bf
21#define DDR_CS0_CONFIG 0x80014302
22#define DDR_TIMING_CFG_0 0x50550004
23#define DDR_TIMING_CFG_1 0xbcb38c56
24#define DDR_TIMING_CFG_2 0x0040d120
25#define DDR_TIMING_CFG_3 0x010e1000
26#define DDR_TIMING_CFG_4 0x00000001
27#define DDR_TIMING_CFG_5 0x03401400
28#define DDR_SDRAM_CFG_2 0x00401010
29#define DDR_SDRAM_MODE 0x00061c60
30#define DDR_SDRAM_MODE_2 0x00180000
31#define DDR_SDRAM_INTERVAL 0x18600618
32#define DDR_DDR_WRLVL_CNTL 0x8655f605
33#define DDR_DDR_WRLVL_CNTL_2 0x05060607
34#define DDR_DDR_WRLVL_CNTL_3 0x05050505
35#define DDR_DDR_CDR1 0x80040000
36#define DDR_DDR_CDR2 0x00000001
37#define DDR_SDRAM_CLK_CNTL 0x02000000
38#define DDR_DDR_ZQ_CNTL 0x89080600
39#define DDR_CS0_CONFIG_2 0
40#define DDR_SDRAM_CFG_MEM_EN 0x80000000
41#define SDRAM_CFG2_D_INIT 0x00000010
42#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
43#define SDRAM_CFG2_FRC_SR 0x80000000
44#define SDRAM_CFG_BI 0x00000001
45
Jianchao Wange5332ba2019-07-19 00:30:01 +030046#ifdef CONFIG_SD_BOOT
Tom Rini7cf9ab72020-06-16 19:06:25 -040047#ifdef CONFIG_NXP_ESBC
Jianchao Wange5332ba2019-07-19 00:30:01 +030048#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Tom Rini7cf9ab72020-06-16 19:06:25 -040049#endif /* ifdef CONFIG_NXP_ESBC */
Jianchao Wange5332ba2019-07-19 00:30:01 +030050
51#define CONFIG_SPL_MAX_SIZE 0x1a000
52#define CONFIG_SPL_STACK 0x1001d000
53#define CONFIG_SPL_PAD_TO 0x1c000
54
55#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
56 CONFIG_SYS_MONITOR_LEN)
57#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
58#define CONFIG_SPL_BSS_START_ADDR 0x80100000
59#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
60
61#ifdef CONFIG_U_BOOT_HDR_SIZE
62/*
63 * HDR would be appended at end of image and copied to DDR along
64 * with U-Boot image. Here u-boot max. size is 512K. So if binary
65 * size increases then increase this size in case of secure boot as
66 * it uses raw U-Boot image instead of FIT image.
67 */
68#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
69#else
70#define CONFIG_SYS_MONITOR_LEN 0x100000
71#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
72#endif
73
Jianchao Wange5332ba2019-07-19 00:30:01 +030074#define PHYS_SDRAM 0x80000000
75#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
76
77#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
78#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79
80#define CONFIG_CHIP_SELECTS_PER_CTRL 4
81
82/* Serial Port */
Jianchao Wange5332ba2019-07-19 00:30:01 +030083#define CONFIG_SYS_NS16550_SERIAL
84#ifndef CONFIG_DM_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE 1
86#endif
87#define CONFIG_SYS_NS16550_CLK get_serial_clock()
88
Jianchao Wange5332ba2019-07-19 00:30:01 +030089/* I2C */
Jianchao Wange5332ba2019-07-19 00:30:01 +030090
91/* EEPROM */
Jianchao Wange5332ba2019-07-19 00:30:01 +030092#define CONFIG_SYS_I2C_EEPROM_NXID
93#define CONFIG_SYS_EEPROM_BUS_NUM 0
Jianchao Wange5332ba2019-07-19 00:30:01 +030094
95/* QSPI */
96#define FSL_QSPI_FLASH_SIZE (1 << 24)
97#define FSL_QSPI_FLASH_NUM 2
98
99/* PCIe */
100#define CONFIG_PCIE1 /* PCIE controller 1 */
101#define CONFIG_PCIE2 /* PCIE controller 2 */
102#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
103#ifdef CONFIG_PCI
104#define CONFIG_PCI_SCAN_SHOW
105#endif
106
107#define CONFIG_LAYERSCAPE_NS_ACCESS
108#define COUNTER_FREQUENCY 12500000
109
110#define CONFIG_HWCONFIG
111#define HWCONFIG_BUFFER_SIZE 256
112
113#define CONFIG_FSL_DEVICE_DISABLE
114
115#define BOOT_TARGET_DEVICES(func) \
116 func(MMC, mmc, 0) \
117 func(USB, usb, 0) \
118 func(DHCP, dhcp, na)
119#include <config_distro_bootcmd.h>
120
121#define CONFIG_EXTRA_ENV_SETTINGS \
122 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
123 "initrd_high=0xffffffff\0" \
Jianchao Wange5332ba2019-07-19 00:30:01 +0300124 "fdt_addr=0x64f00000\0" \
125 "kernel_addr=0x61000000\0" \
126 "kernelheader_addr=0x60800000\0" \
127 "scriptaddr=0x80000000\0" \
128 "scripthdraddr=0x80080000\0" \
129 "fdtheader_addr_r=0x80100000\0" \
130 "kernelheader_addr_r=0x80200000\0" \
131 "kernel_addr_r=0x80008000\0" \
132 "kernelheader_size=0x40000\0" \
133 "fdt_addr_r=0x8f000000\0" \
134 "ramdisk_addr_r=0xa0000000\0" \
135 "load_addr=0x80008000\0" \
136 "kernel_size=0x2800000\0" \
137 "kernel_addr_sd=0x8000\0" \
138 "kernel_size_sd=0x14000\0" \
139 "kernelhdr_addr_sd=0x4000\0" \
140 "kernelhdr_size_sd=0x10\0" \
141 BOOTENV \
142 "boot_scripts=ls1021atsn_boot.scr\0" \
143 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
144 "scan_dev_for_boot_part=" \
145 "part list ${devtype} ${devnum} devplist; " \
146 "env exists devplist || setenv devplist 1; " \
147 "for distro_bootpart in ${devplist}; do " \
148 "if fstype ${devtype} " \
149 "${devnum}:${distro_bootpart} " \
150 "bootfstype; then " \
151 "run scan_dev_for_boot; " \
152 "fi; " \
153 "done\0" \
154 "scan_dev_for_boot=" \
155 "echo Scanning ${devtype} " \
156 "${devnum}:${distro_bootpart}...; " \
157 "for prefix in ${boot_prefixes}; do " \
158 "run scan_dev_for_scripts; " \
159 "run scan_dev_for_extlinux; " \
160 "done;" \
161 "\0" \
162 "boot_a_script=" \
163 "load ${devtype} ${devnum}:${distro_bootpart} " \
164 "${scriptaddr} ${prefix}${script}; " \
165 "env exists secureboot && load ${devtype} " \
166 "${devnum}:${distro_bootpart} " \
167 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
168 "&& esbc_validate ${scripthdraddr};" \
169 "source ${scriptaddr}\0" \
170 "qspi_bootcmd=echo Trying load from qspi..;" \
171 "sf probe && sf read $load_addr " \
172 "$kernel_addr $kernel_size; env exists secureboot " \
173 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
174 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
175 "bootm $load_addr#$board\0" \
176 "sd_bootcmd=echo Trying load from SD ..;" \
177 "mmcinfo && mmc read $load_addr " \
178 "$kernel_addr_sd $kernel_size_sd && " \
179 "env exists secureboot && mmc read $kernelheader_addr_r " \
180 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
181 " && esbc_validate ${kernelheader_addr_r};" \
182 "bootm $load_addr#$board\0"
183
184/* Miscellaneous configurable options */
Alison Wang71477062020-02-03 15:25:19 +0800185#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
186
Jianchao Wange5332ba2019-07-19 00:30:01 +0300187#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
188#define CONFIG_SYS_PBSIZE \
189 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
190#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
191#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
192
Jianchao Wange5332ba2019-07-19 00:30:01 +0300193#define CONFIG_LS102XA_STREAM_ID
194
195#define CONFIG_SYS_INIT_SP_OFFSET \
196 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
197#define CONFIG_SYS_INIT_SP_ADDR \
198 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
199
200#ifdef CONFIG_SPL_BUILD
201#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
202#else
203#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
204#endif
205
206/* Environment */
Jianchao Wange5332ba2019-07-19 00:30:01 +0300207
Jianchao Wange5332ba2019-07-19 00:30:01 +0300208#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
209
210#endif