blob: 8de89a467c29ac159f9032c7d00df9f513ee6eb3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher3c773bb2014-01-25 07:53:48 +01002/*
3 * (C) Copyright 2013
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Based on:
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * Sergej Stepanov <ste@ids.de>
Heiko Schocher3c773bb2014-01-25 07:53:48 +01009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Simon Glassfb64e362020-05-10 11:40:09 -060014#include <linux/stringify.h>
15
Heiko Schocher3c773bb2014-01-25 07:53:48 +010016/*
17 * High Level Configuration Options
18 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +010019#define CONFIG_BOOT_RETRY_TIME 900
20#define CONFIG_BOOT_RETRY_MIN 30
Heiko Schocher3c773bb2014-01-25 07:53:48 +010021#define CONFIG_RESET_TO_RETRY
22
Heiko Schocher3c773bb2014-01-25 07:53:48 +010023#define CONFIG_SYS_SICRH 0x00000000
24#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
25
26#define CONFIG_HWCONFIG
27
Heiko Schocher3c773bb2014-01-25 07:53:48 +010028/*
29 * Definitions for initial stack pointer and data area (in DCACHE )
30 */
31#define CONFIG_SYS_INIT_RAM_LOCK
32#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
33#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
34#define CONFIG_SYS_GBL_DATA_SIZE 0x100
35#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
36 - CONFIG_SYS_GBL_DATA_SIZE)
37#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
38
39/*
Heiko Schocher3c773bb2014-01-25 07:53:48 +010040 * Internal Definitions
41 */
42/*
43 * DDR Setup
44 */
Mario Sixc9f92772019-01-21 09:18:15 +010045#define CONFIG_SYS_SDRAM_BASE 0x00000000
Heiko Schocher3c773bb2014-01-25 07:53:48 +010046
47/*
48 * Manually set up DDR parameters,
49 * as this board has not the SPD connected to I2C.
50 */
51#define CONFIG_SYS_DDR_SIZE 256 /* MB */
52#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
53 0x00010000 |\
54 CSCONFIG_ROW_BIT_13 |\
55 CSCONFIG_COL_BIT_10)
56
57#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
58 CSCONFIG_BANK_BIT_3)
59
60#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
61#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
62 (3 << TIMING_CFG0_WRT_SHIFT) |\
63 (3 << TIMING_CFG0_RRT_SHIFT) |\
64 (3 << TIMING_CFG0_WWT_SHIFT) |\
65 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
66 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
67 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
68 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
69#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
70 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
71 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
72 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
73 (4 << TIMING_CFG1_REFREC_SHIFT) |\
74 (4 << TIMING_CFG1_WRREC_SHIFT) |\
75 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
76 (2 << TIMING_CFG1_WRTORD_SHIFT))
77#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
78 (5 << TIMING_CFG2_CPO_SHIFT) |\
79 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
80 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
81 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
82 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
83 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
84
85#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
86 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
87
88#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
89 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
90 SDRAM_CFG_DBW_32 |\
91 SDRAM_CFG_SDRAM_TYPE_DDR2)
92
93#define CONFIG_SYS_SDRAM_CFG2 0x00401000
94#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
95 (0x0242 << SDRAM_MODE_SD_SHIFT))
96#define CONFIG_SYS_DDR_MODE_2 0x00000000
97#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
98#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
99 DDRCDR_PZ_NOMZ |\
100 DDRCDR_NZ_NOMZ |\
101 DDRCDR_ODT |\
102 DDRCDR_M_ODR |\
103 DDRCDR_Q_DRN)
104
105/*
106 * on-board devices
107 */
108#define CONFIG_TSEC1
109#define CONFIG_TSEC2
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100110
111/*
112 * NOR FLASH setup
113 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100114#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
115#define CONFIG_FLASH_SHOW_PROGRESS 50
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100116
117#define CONFIG_SYS_FLASH_BASE 0xFF800000
118#define CONFIG_SYS_FLASH_SIZE 8
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100119
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100120
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100121#define CONFIG_SYS_MAX_FLASH_SECT 128
122
123#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
124#define CONFIG_SYS_FLASH_WRITE_TOUT 500
125
126/*
127 * NAND FLASH setup
128 */
129#define CONFIG_SYS_NAND_BASE 0xE1000000
130#define CONFIG_SYS_MAX_NAND_DEVICE 1
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100131#define NAND_CACHE_PAGES 64
132
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100133
134/*
135 * MRAM setup
136 */
137#define CONFIG_SYS_MRAM_BASE 0xE2000000
138#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100139
140#define CONFIG_SYS_OR_TIMING_MRAM
141
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100142
143/*
144 * CPLD setup
145 */
146#define CONFIG_SYS_CPLD_BASE 0xE3000000
147#define CONFIG_SYS_CPLD_SIZE 0x8000
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100148
149#define CONFIG_SYS_OR_TIMING_MRAM
150
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100151
152/*
153 * HW-Watchdog
154 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100155#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
156
157/*
158 * I2C setup
159 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100160#define CONFIG_SYS_I2C_RTC_ADDR 0x51
161
162/*
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100163 * Ethernet setup
164 */
165#ifdef CONFIG_TSEC1
166#define CONFIG_HAS_ETH0
167#define CONFIG_TSEC1_NAME "TSEC0"
168#define CONFIG_SYS_TSEC1_OFFSET 0x24000
169#define TSEC1_PHY_ADDR 0x1
170#define TSEC1_FLAGS TSEC_GIGABIT
171#define TSEC1_PHYIDX 0
172#endif
173
174#ifdef CONFIG_TSEC2
175#define CONFIG_HAS_ETH1
176#define CONFIG_TSEC2_NAME "TSEC1"
177#define CONFIG_SYS_TSEC2_OFFSET 0x25000
178#define TSEC2_PHY_ADDR 0x3
179#define TSEC2_FLAGS TSEC_GIGABIT
180#define TSEC2_PHYIDX 0
181#endif
182#define CONFIG_ETHPRIME "TSEC1"
183
184/*
185 * Serial Port
186 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100187#define CONFIG_SYS_NS16550_SERIAL
188#define CONFIG_SYS_NS16550_REG_SIZE 1
189
190#define CONFIG_SYS_BAUDRATE_TABLE \
191 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
192#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
193#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Mario Sixcd677ca2019-01-21 09:17:52 +0100194#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100195
196#define CONFIG_HAS_FSL_DR_USB
197#define CONFIG_SYS_SCCR_USBDRCM 3
198
199/*
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100200 * U-Boot environment setup
201 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100202#define CONFIG_BOOTP_BOOTFILESIZE
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100203
204/*
205 * The reserved memory
206 */
207#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
208#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100209
210/*
211 * Environment Configuration
212 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100213
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100214#define CONFIG_NETDEV eth1
Mario Six790d8442018-03-28 14:38:20 +0200215#define CONFIG_HOSTNAME "ids8313"
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100216#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
217#define CONFIG_BOOTFILE "ids8313/uImage"
218#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
219#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100220#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
221
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100222/* Initial Memory map for Linux*/
223#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
224
225/*
226 * Miscellaneous configurable options
227 */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100228#define CONFIG_SYS_CBSIZE 1024
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100229#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100230
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100231#define CONFIG_LOADS_ECHO
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100232#undef CONFIG_SYS_LOADS_BAUD_CHANGE
233
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100234/* mtdparts command line support */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100235
236#define CONFIG_EXTRA_ENV_SETTINGS \
237 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
238 "ethprime=TSEC1\0" \
239 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
240 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
241 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
242 " +${filesize}; " \
243 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
244 " +${filesize}; " \
245 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
246 " ${filesize}; " \
247 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
248 " +${filesize}; " \
249 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
250 " ${filesize}\0" \
251 "console=ttyS0\0" \
252 "fdtaddr=0x780000\0" \
253 "kernel_addr=ff800000\0" \
254 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
255 "setbootargs=setenv bootargs " \
256 "root=${rootdev} rw console=${console}," \
257 "${baudrate} ${othbootargs}\0" \
258 "setipargs=setenv bootargs root=${rootdev} rw " \
259 "nfsroot=${serverip}:${rootpath} " \
260 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
261 "${netmask}:${hostname}:${netdev}:off " \
262 "console=${console},${baudrate} ${othbootargs}\0" \
263 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400264 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
265 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100266 "\0"
267
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100268/* UBI Support */
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100269
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100270#endif /* __CONFIG_H */