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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc4cbd342005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkc4cbd342005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Meng75574052016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenkc4cbd342005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenkc4cbd342005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenkc4cbd342005-01-09 18:21:42 +000029 * ---
30 */
31
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_CLK 66000000
33#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenkc4cbd342005-01-09 18:21:42 +000034
TsiChungLiewcfa2b482007-08-15 19:41:06 -050035/* Enable Dma Timer */
36#define CONFIG_MCFTMR
wdenkc4cbd342005-01-09 18:21:42 +000037
38/* ---
39 * Define baudrate for UART1 (console output, tftp, ...)
40 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenkc4cbd342005-01-09 18:21:42 +000042 * interface
43 * ---
44 */
45
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_UART_PORT (0)
wdenkc4cbd342005-01-09 18:21:42 +000047
48/* ---
49 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
50 * timeout acc. to your needs
51 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
52 * for 10 sec
53 * ---
54 */
55
56#if 0
wdenkc4cbd342005-01-09 18:21:42 +000057#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
58#endif
59
60/* ---
61 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
62 * bootloader residing in flash ('chainloading'); if you want to use
63 * chainloading or want to compile a u-boot binary that can be loaded into
64 * RAM via BDM set
Wolfgang Denka1be4762008-05-20 16:00:29 +020065 * "#if 0" to "#if 1"
wdenkc4cbd342005-01-09 18:21:42 +000066 * You will need a first stage bootloader then, e. g. colilo or a working BDM
67 * cable (Background Debug Mode)
68 *
69 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
70 *
Wolfgang Denk0708bc62010-10-07 21:51:12 +020071 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenkc4cbd342005-01-09 18:21:42 +000072 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
73 *
74 * ---
75 */
76
77#if 0
78#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
79#endif
80
81/* ---
82 * Configuration for environment
83 * Environment is embedded in u-boot in the second sector of the flash
84 * ---
85 */
86
angelo@sysam.it6312a952015-03-29 22:54:16 +020087#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060088 . = DEFINED(env_offset) ? env_offset : .; \
89 env/embedded.o(.text);
Jon Loeliger37ec35e2007-07-04 22:31:56 -050090
91/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050092 * BOOTP options
93 */
94#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligere54e77a2007-07-10 09:29:01 -050095
TsiChungLiewcfa2b482007-08-15 19:41:06 -050096#ifdef CONFIG_MCFFEC
TsiChung Liewb3162452008-03-30 01:22:13 -050097# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098# define CONFIG_SYS_DISCOVER_PHY
99# define CONFIG_SYS_RX_ETH_BUFFER 8
100# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
102# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500103# define FECDUPLEX FULL
104# define FECSPEED _100BASET
105# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
107# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500108# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500110#endif
wdenkc4cbd342005-01-09 18:21:42 +0000111
112/*
113 *-----------------------------------------------------------------------------
114 * Define user parameters that have to be customized most likely
115 *-----------------------------------------------------------------------------
116 */
117
118/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
119
wdenkc4cbd342005-01-09 18:21:42 +0000120/* The following settings will be contained in the environment block ; if you
121want to use a neutral environment all those settings can be manually set in
122u-boot: 'set' command */
123
124#if 0
125
wdenkc4cbd342005-01-09 18:21:42 +0000126enter a valid image address in flash */
127
wdenkc4cbd342005-01-09 18:21:42 +0000128/* User network settings */
129
wdenkc4cbd342005-01-09 18:21:42 +0000130#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
131#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
132
133#endif
134
wdenkc4cbd342005-01-09 18:21:42 +0000135/*---*/
136
wdenkc4cbd342005-01-09 18:21:42 +0000137/*
138 *-----------------------------------------------------------------------------
139 * End of user parameters to be customized
140 *-----------------------------------------------------------------------------
141 */
142
143/* ---
144 * Defines memory range for test
145 * ---
146 */
147
wdenkc4cbd342005-01-09 18:21:42 +0000148/* ---
149 * Low Level Configuration Settings
150 * (address mappings, register initial values, etc.)
151 * You should know what you are doing if you make changes here.
152 * ---
153 */
154
155/* ---
156 * Base register address
157 * ---
158 */
159
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenkc4cbd342005-01-09 18:21:42 +0000161
162/* ---
163 * System Conf. Reg. & System Protection Reg.
164 * ---
165 */
166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_SCR 0x0003
168#define CONFIG_SYS_SPR 0xffff
wdenkc4cbd342005-01-09 18:21:42 +0000169
170/* ---
171 * Ethernet settings
172 * ---
173 */
174
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_DISCOVER_PHY
176#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenkc4cbd342005-01-09 18:21:42 +0000177
178/*-----------------------------------------------------------------------
179 * Definitions for initial stack pointer and data area (in internal SRAM)
180 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200182#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200183#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc4cbd342005-01-09 18:21:42 +0000185
186/*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc4cbd342005-01-09 18:21:42 +0000190 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkc4cbd342005-01-09 18:21:42 +0000192
193/*
194 *-------------------------------------------------------------------------
195 * RAM SIZE (is defined above)
196 *-----------------------------------------------------------------------
197 */
198
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenkc4cbd342005-01-09 18:21:42 +0000200
201/*
202 *-----------------------------------------------------------------------
203 */
204
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkc4cbd342005-01-09 18:21:42 +0000206
207#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkc4cbd342005-01-09 18:21:42 +0000209#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkc4cbd342005-01-09 18:21:42 +0000211#endif
212
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_MONITOR_LEN 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkc4cbd342005-01-09 18:21:42 +0000215
216/*
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization ??
220 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc4cbd342005-01-09 18:21:42 +0000222
223/*-----------------------------------------------------------------------
224 * FLASH organization
225 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
227#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenkc4cbd342005-01-09 18:21:42 +0000228
229/*-----------------------------------------------------------------------
230 * Cache Configuration
231 */
wdenkc4cbd342005-01-09 18:21:42 +0000232
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600233#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200234 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600235#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200236 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600237#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
238#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
239 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
240 CF_ACR_EN | CF_ACR_SM_ALL)
241#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
242 CF_CACR_DISD | CF_CACR_INVI | \
243 CF_CACR_CEIB | CF_CACR_DCM | \
244 CF_CACR_EUSP)
245
wdenkc4cbd342005-01-09 18:21:42 +0000246/*-----------------------------------------------------------------------
wdenkc4cbd342005-01-09 18:21:42 +0000247 * LED config
248 */
249#define LED_STAT_0 0xffff /*all LEDs off*/
250#define LED_STAT_1 0xfffe
251#define LED_STAT_2 0xfffd
252#define LED_STAT_3 0xfffb
253#define LED_STAT_4 0xfff7
254#define LED_STAT_5 0xffef
255#define LED_STAT_6 0xffdf
256#define LED_STAT_7 0xff00 /*all LEDs on*/
257
258/*-----------------------------------------------------------------------
259 * Port configuration (GPIO)
260 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenkc4cbd342005-01-09 18:21:42 +0000262GPIO*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenkc4cbd342005-01-09 18:21:42 +0000264(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
266#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenkc4cbd342005-01-09 18:21:42 +0000267configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
269#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
270#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenkc4cbd342005-01-09 18:21:42 +0000271
272#endif /* _CONFIG_COBRA5272_H */