Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2017-2018 NXP |
| 4 | * Copyright 2019 Siemens AG |
| 5 | */ |
| 6 | |
| 7 | #ifndef __IMX8X_CAPRICORN_H |
| 8 | #define __IMX8X_CAPRICORN_H |
| 9 | |
| 10 | #include <linux/sizes.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | |
| 13 | #include "siemens-env-common.h" |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 14 | |
| 15 | /* SPL config */ |
| 16 | #ifdef CONFIG_SPL_BUILD |
| 17 | |
| 18 | #define CONFIG_SPL_MAX_SIZE (124 * 1024) |
| 19 | #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 20 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 21 | #define CONFIG_SPL_STACK 0x013E000 |
| 22 | #define CONFIG_SPL_BSS_START_ADDR 0x00128000 |
| 23 | #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ |
| 24 | #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 |
| 25 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ |
| 26 | #define CONFIG_MALLOC_F_ADDR 0x00120000 |
| 27 | |
| 28 | #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE |
| 29 | #define CONFIG_SPL_ABORT_ON_RAW_IMAGE |
| 30 | |
| 31 | #endif /* CONFIG_SPL_BUILD */ |
| 32 | |
| 33 | #define CONFIG_FACTORYSET |
| 34 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 35 | #define CONFIG_REMAKE_ELF |
| 36 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 37 | /* ENET Config */ |
| 38 | #define CONFIG_FEC_XCV_TYPE RMII |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 39 | |
| 40 | /* ENET1 connects to base board and MUX with ESAI */ |
| 41 | #define CONFIG_FEC_ENET_DEV 1 |
| 42 | #define CONFIG_FEC_MXC_PHYADDR 0x0 |
| 43 | #define CONFIG_ETHPRIME "eth1" |
| 44 | |
| 45 | /* I2C Configuration */ |
| 46 | #ifndef CONFIG_SPL_BUILD |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 47 | /* EEPROM */ |
| 48 | #define EEPROM_I2C_BUS 0 /* I2C0 */ |
| 49 | #define EEPROM_I2C_ADDR 0x50 |
| 50 | /* PCA9552 */ |
| 51 | #define PCA9552_1_I2C_BUS 1 /* I2C1 */ |
| 52 | #define PCA9552_1_I2C_ADDR 0x60 |
| 53 | #endif /* !CONFIG_SPL_BUILD */ |
| 54 | |
| 55 | /* AHAB */ |
| 56 | #ifdef CONFIG_AHAB_BOOT |
| 57 | #define AHAB_ENV "sec_boot=yes\0" |
| 58 | #else |
| 59 | #define AHAB_ENV "sec_boot=no\0" |
| 60 | #endif |
| 61 | |
| 62 | #define MFG_ENV_SETTINGS_DEFAULT \ |
| 63 | "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ |
| 64 | "rdinit=/linuxrc " \ |
| 65 | "clk_ignore_unused "\ |
| 66 | "\0" \ |
| 67 | "kboot=booti\0"\ |
| 68 | "bootcmd_mfg=run mfgtool_args;" \ |
| 69 | "if iminfo ${initrd_addr}; then " \ |
| 70 | "if test ${tee} = yes; then " \ |
| 71 | "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ |
| 72 | "else " \ |
| 73 | "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \ |
| 74 | "fi; " \ |
| 75 | "else " \ |
| 76 | "echo \"Run fastboot ...\"; fastboot 0; " \ |
| 77 | "fi;\0" |
| 78 | |
| 79 | /* Boot M4 */ |
| 80 | #define M4_BOOT_ENV \ |
| 81 | "m4_0_image=m4_0.bin\0" \ |
| 82 | "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \ |
| 83 | "${loadaddr} ${m4_0_image}\0" \ |
| 84 | "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ |
| 85 | |
| 86 | #define CONFIG_MFG_ENV_SETTINGS \ |
| 87 | MFG_ENV_SETTINGS_DEFAULT \ |
| 88 | "initrd_addr=0x83100000\0" \ |
| 89 | "initrd_high=0xffffffffffffffff\0" \ |
| 90 | "emmc_dev=0\0" |
| 91 | |
| 92 | /* Initial environment variables */ |
| 93 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 94 | CONFIG_MFG_ENV_SETTINGS \ |
| 95 | M4_BOOT_ENV \ |
| 96 | AHAB_ENV \ |
| 97 | ENV_COMMON \ |
| 98 | "script=boot.scr\0" \ |
| 99 | "image=Image\0" \ |
| 100 | "panel=NULL\0" \ |
| 101 | "console=ttyLP2\0" \ |
| 102 | "fdt_addr=0x83000000\0" \ |
| 103 | "fdt_high=0xffffffffffffffff\0" \ |
| 104 | "cntr_addr=0x88000000\0" \ |
| 105 | "cntr_file=os_cntr_signed.bin\0" \ |
| 106 | "initrd_addr=0x83800000\0" \ |
| 107 | "initrd_high=0xffffffffffffffff\0" \ |
| 108 | "netdev=eth0\0" \ |
| 109 | "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \ |
| 110 | "hostname=capricorn\0" \ |
| 111 | ENV_EMMC \ |
| 112 | ENV_NET |
| 113 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 114 | /* Default location for tftp and bootm */ |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 115 | #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 |
| 116 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 117 | /* On CCP board, USDHC1 is for eMMC */ |
| 118 | #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 119 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 120 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| 121 | #define PHYS_SDRAM_1 0x80000000 |
| 122 | #define PHYS_SDRAM_2 0x880000000 |
| 123 | /* DDR3 board total DDR is 1 GB */ |
| 124 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ |
| 125 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ |
| 126 | |
Anatolij Gustschin | 49234a3 | 2020-01-07 16:37:42 +0100 | [diff] [blame] | 127 | /* Console buffer and boot args */ |
| 128 | #define CONFIG_SYS_CBSIZE 2048 |
| 129 | #define CONFIG_SYS_MAXARGS 64 |
| 130 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 131 | |
| 132 | /* Generic Timer Definitions */ |
| 133 | #define COUNTER_FREQUENCY 8000000 /* 8MHz */ |
| 134 | |
| 135 | #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 |
| 136 | #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ |
| 137 | |
| 138 | #endif /* __IMX8X_CAPRICORN_H */ |