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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -06002/*
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
4 *
Alison Wange573de22012-03-25 19:18:14 +00005 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew6f8a0a32008-01-14 17:23:08 -06006 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -06007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5373EVB_H
14#define _M5373EVB_H
15
Simon Glassfb64e362020-05-10 11:40:09 -060016#include <linux/stringify.h>
17
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060018/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060022
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060024
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060025#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
26
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020027#define CONFIG_SYS_UNIFY_CACHE
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060028
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060029#ifdef CONFIG_MCFFEC
TsiChung Liewb3162452008-03-30 01:22:13 -050030# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031# define CONFIG_SYS_DISCOVER_PHY
32# define CONFIG_SYS_RX_ETH_BUFFER 8
33# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
35# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060036# define FECDUPLEX FULL
37# define FECSPEED _100BASET
38# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
40# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060041# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060043#endif
44
45#define CONFIG_MCFRTC
46#undef RTC_DEBUG
47
48/* Timer */
49#define CONFIG_MCFTMR
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060050
51/* I2C */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060052
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060053#ifdef CONFIG_MCFFEC
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060054# define CONFIG_IPADDR 192.162.1.2
55# define CONFIG_NETMASK 255.255.255.0
56# define CONFIG_SERVERIP 192.162.1.1
57# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060058#endif /* FEC_ENET */
59
Mario Six790d8442018-03-28 14:38:20 +020060#define CONFIG_HOSTNAME "M5373EVB"
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060061#define CONFIG_EXTRA_ENV_SETTINGS \
62 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +020063 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060064 "u-boot=u-boot.bin\0" \
65 "load=tftp ${loadaddr) ${u-boot}\0" \
66 "upd=run load; run prog\0" \
Jason Jinded4eb42011-08-19 10:10:40 +080067 "prog=prot off 0 3ffff;" \
68 "era 0 3ffff;" \
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060069 "cp.b ${loadaddr} 0 ${filesize};" \
70 "save\0" \
71 ""
72
73#define CONFIG_PRAM 512 /* 512 KB */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_CLK 80000000
76#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060077
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020078#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060079
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060081
82/*
83 * Low Level Configuration Settings
84 * (address mappings, register initial values, etc.)
85 * You should know what you are doing if you make changes here.
86 */
87/*-----------------------------------------------------------------------
88 * Definitions for initial stack pointer and data area (in DPRAM)
89 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020091#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk0191e472010-10-26 14:34:52 +020093#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew6f8a0a32008-01-14 17:23:08 -060095
96/*-----------------------------------------------------------------------
97 * Start addresses for the final memory configuration
98 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600100 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_SDRAM_BASE 0x40000000
102#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
103#define CONFIG_SYS_SDRAM_CFG1 0x53722730
104#define CONFIG_SYS_SDRAM_CFG2 0x56670000
105#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
106#define CONFIG_SYS_SDRAM_EMOD 0x40010000
107#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600108
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
110#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600113
114/*
115 * For booting Linux, the board info and command line data
116 * have to be in the first 8 MB of memory, since this is
117 * the maximum mapped by the Linux kernel during initialization ??
118 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew25a00632009-01-27 12:57:47 +0000120#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600121
122/*-----------------------------------------------------------------------
123 * FLASH organization
124 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
127# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600129#endif
130
Alison Wange573de22012-03-25 19:18:14 +0000131#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132# define CONFIG_SYS_MAX_NAND_DEVICE 1
133# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
134# define CONFIG_SYS_NAND_SIZE 1
135# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600136# define NAND_ALLOW_ERASE_ALL 1
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600137#endif
138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600140
141/* Configuration for environment
142 * Environment is embedded in u-boot in the second sector of the flash
143 */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600144
angelo@sysam.it6312a952015-03-29 22:54:16 +0200145#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -0600146 . = DEFINED(env_offset) ? env_offset : .; \
147 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +0200148
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600149/*-----------------------------------------------------------------------
150 * Cache Configuration
151 */
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600152
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600153#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200154 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600155#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200156 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600157#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
158#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
159 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
160 CF_ACR_EN | CF_ACR_SM_ALL)
161#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
162 CF_CACR_DCM_P)
163
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600164/*-----------------------------------------------------------------------
165 * Chipselect bank definitions
166 */
167/*
168 * CS0 - NOR Flash 1, 2, 4, or 8MB
169 * CS1 - CompactFlash and registers
170 * CS2 - NAND Flash 16, 32, or 64MB
171 * CS3 - Available
172 * CS4 - Available
173 * CS5 - Available
174 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_CS0_BASE 0
176#define CONFIG_SYS_CS0_MASK 0x007f0001
177#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600178
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_CS1_BASE 0x10000000
180#define CONFIG_SYS_CS1_MASK 0x001f0001
181#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600182
Alison Wange573de22012-03-25 19:18:14 +0000183#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_CS2_BASE 0x20000000
Alison Wange573de22012-03-25 19:18:14 +0000185#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600187#endif
188
189#endif /* _M5373EVB_H */