| Niklaus Giger | e62b4f6 | 2007-07-27 11:25:31 +0200 | [diff] [blame] | 1 | HCU5 configuration details and startup sequence |
| 2 | |
| 3 | (C) Copyright 2007 Netstal Maschinen AG |
| 4 | Niklaus Giger (Niklaus.Giger@netstal.com) |
| 5 | |
| 6 | TODO: |
| 7 | ----- |
| 8 | - Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT ! |
| 9 | - Does not occur if both EMAC are connected |
| 10 | - Fix RTS/CTS problem (HW?) |
| 11 | CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after |
| 12 | Switching to interrupt driven serial input mode |
| 13 | - Make vxWorks start from u-boot. Possible reasons |
| 14 | - Does vxWorks need an entry for the Machine Check interrupt like this |
| 15 | tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ? |
| 16 | |
| 17 | Caveats: |
| 18 | -------- |
| 19 | Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c) |
| 20 | see hcu5.c. |
| 21 | |
| 22 | |
| 23 | Memory Bank 0 -- Flash chip |
| 24 | --------------------------- |
| 25 | |
| 26 | 0xfff00000 - 0xffffffff |
| 27 | |
| 28 | The flash chip is really only 512Kbytes, but the high address bit of |
| 29 | the 1Meg region is ignored, so the flash is replicated through the |
| 30 | region. Thus, this is consistent with a flash base address 0xfff80000. |
| 31 | |
| 32 | The placement at the end is to be consistent with reset behavior, |
| 33 | where the processor itself initially uses this bus to load the branch |
| 34 | vector and start running. |
| 35 | |
| 36 | On-Chip Memory |
| 37 | -------------- |
| 38 | |
| 39 | 0xe0010000- 0xe0013fff CFG_OCM_BASE |
| 40 | The 440EPx includes a 16K on-chip memory that can be placed however |
| 41 | software chooses. |
| 42 | |
| 43 | Internal Peripherals |
| 44 | -------------------- |
| 45 | |
| 46 | 0xef600300 - 0xef6008ff |
| 47 | |
| 48 | These are scattered various peripherals internal to the PPC440EPX |
| 49 | chip. |
| 50 | |
| 51 | Chip-Select 2: Flash Memory |
| 52 | --------------------------- |
| 53 | |
| 54 | Not used |
| 55 | |
| 56 | Chip-Select 3: CAN Interface |
| 57 | ---------------------------- |
| 58 | 0xc800000: 2 Intel 82527 CAN-Controller |
| 59 | |
| 60 | |
| 61 | Chip-Select 4: IMC-bus standard |
| 62 | ------------------------------- |
| 63 | |
| 64 | 0xcc00000: Netstal specific IO-Bus |
| 65 | |
| 66 | |
| 67 | Chip-Select 5: IMC-bus fast (inactive) |
| 68 | -------------------------------------- |
| 69 | |
| 70 | 0xce00000: Netstal specific IO-Bus (fast, but not yet used) |
| 71 | |
| 72 | |
| 73 | Memory Bank 1 -- DDR2 |
| 74 | ------------------------------------- |
| 75 | |
| 76 | 0x00000000 - 0xfffffff # Default 256 MB |
| 77 | |
| 78 | PCI ?? |
| 79 | |
| 80 | USB ?? |
| 81 | Only USB_STORAGE is enabled to load vxWorks |
| 82 | from a memory stick. |
| 83 | |
| 84 | System-LEDs ??? (Analog zu HCU4 ???) |
| 85 | |
| 86 | Startup sequence |
| 87 | ---------------- |
| 88 | |
| 89 | (cpu/ppc4xx/resetvec.S) |
| 90 | depending on configs option |
| 91 | call _start_440 _start_pci oder _start |
| 92 | |
| 93 | (cpu/ppc4xx/start.S) |
| 94 | |
| 95 | _start_440: |
| 96 | initialize register like |
| 97 | CCR0 |
| 98 | debug |
| 99 | setup interrupt vectors |
| 100 | configure cache regions |
| 101 | clear and setup TLB |
| 102 | enable internal RAM |
| 103 | jump start_ram |
| 104 | which in turn will jump to start |
| 105 | _start: |
| 106 | Clear and set up some registers. |
| 107 | Debug setup |
| 108 | Setup the internal SRAM |
| 109 | Setup the stack in internal SRAM |
| 110 | setup stack pointer (r1) |
| 111 | setup GOT |
| 112 | call cpu_init_f /* run low-level CPU init code (from Flash) */ |
| 113 | |
| 114 | call cpu_init_f |
| 115 | board_init_f: (lib_ppc\board.c) |
| 116 | init_sequence defines a list of function to be called |
| 117 | board_early_init_f: (board/netstal/hcu5/hcu5.c) |
| 118 | We are using Bootstrap-Option A |
| 119 | if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot |
| 120 | Setup the GPIO pins |
| 121 | Setup the interrupt controller polarities, triggers, etc. |
| 122 | Ethernet, PCI, USB enable |
| 123 | setup BOOT FLASH (Chip timing) |
| 124 | init_baudrate, |
| 125 | serial_init |
| 126 | checkcpu |
| 127 | misc_init_f #ifdef |
| 128 | init_func_i2c #ifdef |
| 129 | post_init_f #ifdef |
| 130 | init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c |
| 131 | (EYE function removed!!) |
| 132 | test_dram call |
| 133 | |
| 134 | * Reserve memory at end of RAM for (top down in that order): |
| 135 | * - kernel log buffer |
| 136 | * - protected RAM |
| 137 | * - LCD framebuffer |
| 138 | * - monitor code |
| 139 | * - board info struct |
| 140 | Save local variables to board info struct |
| 141 | call relocate_code() does not return |
| 142 | relocate_code: (cpu/ppc4xx/start.S) |
| 143 | ------------------------------------------------------- |
| 144 | From now on our copy is in RAM and we will run from there, |
| 145 | starting with board_init_r |
| 146 | ------------------------------------------------------- |
| 147 | board_init_r: (lib_ppc\board.c) |
| 148 | setup bd function pointers |
| 149 | trap_init |
| 150 | flash_init: (board/netstal/hcu5/flash.c) |
| 151 | /* setup for u-boot erase, update */ |
| 152 | setup bd flash info |
| 153 | cpu_init_r: (cpu/ppc4xx/cpu_init.c) |
| 154 | peripheral chip select in using defines like |
| 155 | CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h |
| 156 | mem_malloc_init |
| 157 | malloc_bin_reloc |
| 158 | spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) |
| 159 | env_relocated |
| 160 | misc_init_r(bd): (board/netstal/hcu5.c) |
| 161 | ethaddr mit serial number ergänzen |
| 162 | Then we will somehow go into the command loop |
| 163 | |
| 164 | Most of the HW specific code for the HCU5 may be found in |
| 165 | include/configs/hcu5.h |
| 166 | board/netstal/hcu5/* |
| 167 | cpu/ppc4xx/* |
| 168 | lib_ppc/* |
| 169 | include/ppc440.h |
| 170 | |
| 171 | Drivers for serial etc are found under drivers/ |
| 172 | |
| 173 | Don't ask question if you did not look at the README !! |
| 174 | Most CFG_* and CONFIG_* switches are mentioned/explained there. |