| Madalin Bucur | ee7bc98 | 2020-04-30 16:00:03 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ] |
| 4 | * |
| 5 | * Copyright 2012 - 2015 Freescale Semiconductor Inc. |
| 6 | * Copyright 2020 NXP |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | fman0: fman@400000 { |
| 11 | #address-cells = <1>; |
| 12 | #size-cells = <1>; |
| 13 | cell-index = <0>; |
| 14 | compatible = "fsl,fman"; |
| 15 | ranges = <0 0x400000 0xfe000>; |
| 16 | reg = <0x400000 0xfe000>; |
| 17 | interrupts = <96 2 0 0>, <16 2 1 1>; |
| 18 | clocks = <&clockgen 3 0>; |
| 19 | clock-names = "fmanclk"; |
| 20 | fsl,qman-channel-range = <0x800 0x10>; |
| 21 | ptimer-handle = <&ptp_timer0>; |
| 22 | |
| 23 | muram@0 { |
| 24 | compatible = "fsl,fman-muram"; |
| 25 | reg = <0x0 0x30000>; |
| 26 | }; |
| 27 | |
| 28 | fman0_oh_0x2: port@82000 { |
| 29 | cell-index = <0x2>; |
| 30 | compatible = "fsl,fman-v3-port-oh"; |
| 31 | reg = <0x82000 0x1000>; |
| 32 | }; |
| 33 | |
| 34 | fman0_oh_0x3: port@83000 { |
| 35 | cell-index = <0x3>; |
| 36 | compatible = "fsl,fman-v3-port-oh"; |
| 37 | reg = <0x83000 0x1000>; |
| 38 | }; |
| 39 | |
| 40 | fman0_oh_0x4: port@84000 { |
| 41 | cell-index = <0x4>; |
| 42 | compatible = "fsl,fman-v3-port-oh"; |
| 43 | reg = <0x84000 0x1000>; |
| 44 | }; |
| 45 | |
| 46 | fman0_oh_0x5: port@85000 { |
| 47 | cell-index = <0x5>; |
| 48 | compatible = "fsl,fman-v3-port-oh"; |
| 49 | reg = <0x85000 0x1000>; |
| 50 | }; |
| 51 | |
| 52 | mdio0: mdio@fc000 { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <0>; |
| 55 | compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; |
| 56 | reg = <0xfc000 0x1000>; |
| 57 | }; |
| 58 | |
| 59 | xmdio0: mdio@fd000 { |
| 60 | #address-cells = <1>; |
| 61 | #size-cells = <0>; |
| 62 | compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; |
| 63 | reg = <0xfd000 0x1000>; |
| 64 | }; |
| 65 | }; |
| 66 | |
| 67 | ptp_timer0: ptp-timer@4fe000 { |
| 68 | compatible = "fsl,fman-ptp-timer"; |
| 69 | reg = <0x4fe000 0x1000>; |
| 70 | interrupts = <96 2 0 0>; |
| 71 | clocks = <&clockgen 3 0>; |
| 72 | }; |