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git01.mediatek.com / filogic / uboot / d693b1e9e7a57b115aa48df0a3de743ca56a25ff / . / arch / arm / dts / tegra20-harmony.dts
blob: e6e42295e216620e7ad28dbd3ad0245410de30b4 [file] [log] [blame]
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6 model = "NVIDIA Tegra20 Harmony evaluation board";
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uartd;
11 };
12
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]15 usb1 = "/usb@c5004000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]16 sdhci0 = "/sdhci@c8000600";
17 sdhci1 = "/sdhci@c8000200";
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]18 };
19
20 memory {
21 reg = <0x00000000 0x40000000>;
22 };
23
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]24 host1x {
25 status = "okay";
26 dc@54200000 {
27 status = "okay";
28 rgb {
29 status = "okay";
30 nvidia,panel = <&lcd_panel>;
31 };
32 };
33 };
34
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]35 serial@70006300 {
36 clock-frequency = < 216000000 >;
37 };
38
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]39 nand-controller@70008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]40 nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
Allen Martin0398dcb2013-01-16 13:12:24 +0000[diff] [blame]41 nvidia,width = <8>;
42 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
43 nand@0 {
44 reg = <0>;
45 compatible = "hynix,hy27uf4g2b", "nand-flash";
46 };
47 };
48
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]49 i2c@7000c000 {
50 status = "disabled";
51 };
52
53 i2c@7000c400 {
54 status = "disabled";
55 };
56
57 i2c@7000c500 {
58 status = "disabled";
59 };
60
61 i2c@7000d000 {
62 status = "disabled";
63 };
64
65 usb@c5000000 {
66 status = "disabled";
67 };
68
69 usb@c5004000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]70 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]71 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]72
73 sdhci@c8000200 {
74 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]75 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
76 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
77 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]78 bus-width = <4>;
79 };
80
81 sdhci@c8000600 {
82 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]83 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
84 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
85 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]86 bus-width = <8>;
87 };
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]88
89 lcd_panel: panel {
90 clock = <42430000>;
91 xres = <1024>;
92 yres = <600>;
93 left-margin = <138>;
94 right-margin = <34>;
95 hsync-len = <136>;
96 lower-margin = <4>;
97 upper-margin = <21>;
98 vsync-len = <4>;
99 hsync-active-high;
100 vsyncx-active-high;
101 nvidia,bits-per-pixel = <16>;
102 nvidia,pwm = <&pwm 0 0>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]103 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
104 GPIO_ACTIVE_HIGH>;
105 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
106 GPIO_ACTIVE_HIGH>;
107 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
108 GPIO_ACTIVE_HIGH>;
109 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
110 GPIO_ACTIVE_HIGH>;
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]111 nvidia,panel-timings = <0 0 200 0 0>;
112 };
Stephen Warrenc7382852012-05-21 10:04:27 +0000[diff] [blame]113};