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git01.mediatek.com / filogic / uboot / d67ad6e3a9550f72dc97c30a12515e7b522799e5 / . / include / zynqmp_tap_delay.h
blob: 1c1e3e7deedd4abb6feab31fa972fc09c96d638c [file] [log] [blame]
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx ZynqMP SoC Tap Delay Programming
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7
8#ifndef __ZYNQMP_TAP_DELAY_H__
9#define __ZYNQMP_TAP_DELAY_H__
10
11#ifdef CONFIG_ARCH_ZYNQMP
12void zynqmp_dll_reset(u8 deviceid);
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]13void arasan_zynqmp_set_in_tapdelay(u8 device_id, u32 itap_delay);
14void arasan_zynqmp_set_out_tapdelay(u8 device_id, u32 otap_delay);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]15#else
16inline void zynqmp_dll_reset(u8 deviceid) {}
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]17inline void arasan_zynqmp_set_in_tapdelay(u8 device_id, u32 itap_delay) {}
18inline void arasan_zynqmp_set_out_tapdelay(u8 device_id, u32 otap_delay) {}
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]19#endif
20
21#endif