Blame - include/configs/theadorable.h - filogic/uboot

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Tom Rini	10e4779	2018-05-06 17:58:06 -0400	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	2	/*
				3	* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	4	*/
				5
				6	#ifndef _CONFIG_THEADORABLE_H
				7	#define _CONFIG_THEADORABLE_H
				8
				9	/*
				10	* High Level Configuration Options (easy to change)
				11	*/
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	12
				13	/*
				14	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
				15	* for DDR ECC byte filling in the SPL before loading the main
				16	* U-Boot into it.
				17	*/
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	18	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
				19
				20	/*
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	21	* The debugging version enables USB support via defconfig.
				22	* This version should also enable all other non-production
				23	* interfaces / features.
				24	*/
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	25
				26	/* I2C */
Simon Glass	0529b59	2021-07-10 21:14:32 -0600	[diff] [blame]	27	#define CONFIG_SYS_I2C_LEGACY
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	28	#define CONFIG_SYS_I2C_MVTWSI
				29	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese	07b5e04	2016-04-08 15:58:29 +0200	[diff] [blame]	30	#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	31	#define CONFIG_SYS_I2C_SLAVE 0x0
				32	#define CONFIG_SYS_I2C_SPEED 100000
				33
				34	/* USB/EHCI configuration */
				35	#define CONFIG_EHCI_IS_TDI
				36	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
				37
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	38	/* Environment in SPI NOR flash */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	39
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	40	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
				41
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	42	/* Keep device tree and initrd in lower memory so the kernel can access them */
				43	#define CONFIG_EXTRA_ENV_SETTINGS \
				44	"fdt_high=0x10000000\0" \
				45	"initrd_high=0x10000000\0"
				46
				47	/* SATA support */
				48	#define CONFIG_SYS_SATA_MAX_DEVICE 1
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	49	#define CONFIG_LBA48
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	50
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	51	/* Enable LCD and reserve 512KB from top of memory*/
				52	#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
				53
Stefan Roese	f054758	2016-02-12 14:24:07 +0100	[diff] [blame]	54	/* FPGA programming support */
Stefan Roese	f054758	2016-02-12 14:24:07 +0100	[diff] [blame]	55	#define CONFIG_FPGA_STRATIX_V
				56
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	57	/*
Stefan Roese	1a4e980	2016-04-07 10:48:14 +0200	[diff] [blame]	58	* Bootcounter
				59	*/
Stefan Roese	1a4e980	2016-04-07 10:48:14 +0200	[diff] [blame]	60	/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
				61	#define BOOTCOUNT_ADDR 0x1000
				62
				63	/*
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	64	* mv-common.h should be defined after CMD configs since it used them
				65	* to enable certain macros
				66	*/
				67	#include "mv-common.h"
				68
				69	/*
				70	* Memory layout while starting into the bin_hdr via the
				71	* BootROM:
				72	*
				73	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
				74	* 0x4000.4030 bin_hdr start address
				75	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
				76	* 0x4007.fffc BootROM stack top
				77	*
				78	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
				79	* L2 cache thus cannot be used.
				80	*/
				81
				82	/* SPL */
				83	/* Defines for SPL */
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	84	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
				85
				86	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
				87	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
				88
				89	#ifdef CONFIG_SPL_BUILD
				90	#define CONFIG_SYS_MALLOC_SIMPLE
				91	#endif
				92
				93	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
				94	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
				95
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	96	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
				97	#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
				98
				99	#endif /* _CONFIG_THEADORABLE_H */