blob: 3aa8c641f9ab5c59b85516920483c02a3d787ba9 [file] [log] [blame]
Peng Fan525c8762019-08-19 07:54:04 +00001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <clk-uclass.h>
10#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Peng Fan525c8762019-08-19 07:54:04 +000012#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <dt-bindings/clock/imx8mm-clock.h>
15
16#include "clk.h"
17
18#define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44};
45
46static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48};
49
50static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mm_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
54};
55
56static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mm_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
60};
61
62static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mm_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
66};
67
68static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
76 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
77
Frieder Schrempf2d82cf82019-10-23 16:36:44 +000078static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
Peng Fan525c8762019-08-19 07:54:04 +000079 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
80
81static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
82 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
83
Peng Fanee5515d2019-10-22 03:29:48 +000084#ifndef CONFIG_SPL_BUILD
85static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
86 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
87
88static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
89 "clk_ext3", "clk_ext4", "video_pll1_out", };
90
91static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
92 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
93#endif
94
Peng Fan525c8762019-08-19 07:54:04 +000095static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
96 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
97
Ye Li0321edb2020-04-19 02:22:09 -070098static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
99 "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
100
Peng Fan525c8762019-08-19 07:54:04 +0000101static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
102 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
103
104static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
105 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
106
107static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
108 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
109
110static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
111 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
112
113static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
114 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
115
116static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
117 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
118
119static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
120 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
121
122static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
123 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
124
Peng Fan2dff8792020-06-27 15:49:28 +0800125static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
126 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
127
Ye Li0321edb2020-04-19 02:22:09 -0700128static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
129 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
130
131static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
132 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
133
Frieder Schrempf339beba2021-06-07 14:36:43 +0200134static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
135 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
136
137static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
138 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
139
140static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
141 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
142
Peng Fan525c8762019-08-19 07:54:04 +0000143static ulong imx8mm_clk_get_rate(struct clk *clk)
144{
145 struct clk *c;
146 int ret;
147
148 debug("%s(#%lu)\n", __func__, clk->id);
149
150 ret = clk_get_by_id(clk->id, &c);
151 if (ret)
152 return ret;
153
154 return clk_get_rate(c);
155}
156
157static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
158{
159 struct clk *c;
160 int ret;
161
162 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
163
164 ret = clk_get_by_id(clk->id, &c);
165 if (ret)
166 return ret;
167
168 return clk_set_rate(c, rate);
169}
170
171static int __imx8mm_clk_enable(struct clk *clk, bool enable)
172{
173 struct clk *c;
174 int ret;
175
176 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
177
178 ret = clk_get_by_id(clk->id, &c);
179 if (ret)
180 return ret;
181
182 if (enable)
183 ret = clk_enable(c);
184 else
185 ret = clk_disable(c);
186
187 return ret;
188}
189
190static int imx8mm_clk_disable(struct clk *clk)
191{
192 return __imx8mm_clk_enable(clk, 0);
193}
194
195static int imx8mm_clk_enable(struct clk *clk)
196{
197 return __imx8mm_clk_enable(clk, 1);
198}
199
Peng Fan7adf5872019-10-22 03:29:51 +0000200static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
201{
202 struct clk *c, *cp;
203 int ret;
204
205 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
206
207 ret = clk_get_by_id(clk->id, &c);
208 if (ret)
209 return ret;
210
211 ret = clk_get_by_id(parent->id, &cp);
212 if (ret)
213 return ret;
214
Peng Fan6088c512020-06-27 15:48:04 +0800215 ret = clk_set_parent(c, cp);
216 c->dev->parent = cp->dev;
217
218 return ret;
Peng Fan7adf5872019-10-22 03:29:51 +0000219}
220
Peng Fan525c8762019-08-19 07:54:04 +0000221static struct clk_ops imx8mm_clk_ops = {
222 .set_rate = imx8mm_clk_set_rate,
223 .get_rate = imx8mm_clk_get_rate,
224 .enable = imx8mm_clk_enable,
225 .disable = imx8mm_clk_disable,
Peng Fan7adf5872019-10-22 03:29:51 +0000226 .set_parent = imx8mm_clk_set_parent,
Peng Fan525c8762019-08-19 07:54:04 +0000227};
228
229static int imx8mm_clk_probe(struct udevice *dev)
230{
231 void __iomem *base;
232
233 base = (void *)ANATOP_BASE_ADDR;
234
235 clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
236 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
237 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
238 clk_dm(IMX8MM_ARM_PLL_REF_SEL,
239 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
240 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
241 clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
242 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
243 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
244 clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
245 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
246 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
247 clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
248 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
249 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
250
251 clk_dm(IMX8MM_DRAM_PLL,
252 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
253 base + 0x50, &imx8mm_dram_pll));
254 clk_dm(IMX8MM_ARM_PLL,
255 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
256 base + 0x84, &imx8mm_arm_pll));
257 clk_dm(IMX8MM_SYS_PLL1,
258 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
259 base + 0x94, &imx8mm_sys_pll));
260 clk_dm(IMX8MM_SYS_PLL2,
261 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
262 base + 0x104, &imx8mm_sys_pll));
263 clk_dm(IMX8MM_SYS_PLL3,
264 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
265 base + 0x114, &imx8mm_sys_pll));
266
267 /* PLL bypass out */
268 clk_dm(IMX8MM_DRAM_PLL_BYPASS,
269 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
270 dram_pll_bypass_sels,
271 ARRAY_SIZE(dram_pll_bypass_sels),
272 CLK_SET_RATE_PARENT));
273 clk_dm(IMX8MM_ARM_PLL_BYPASS,
274 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
275 arm_pll_bypass_sels,
276 ARRAY_SIZE(arm_pll_bypass_sels),
277 CLK_SET_RATE_PARENT));
278 clk_dm(IMX8MM_SYS_PLL1_BYPASS,
279 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
280 sys_pll1_bypass_sels,
281 ARRAY_SIZE(sys_pll1_bypass_sels),
282 CLK_SET_RATE_PARENT));
283 clk_dm(IMX8MM_SYS_PLL2_BYPASS,
284 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
285 sys_pll2_bypass_sels,
286 ARRAY_SIZE(sys_pll2_bypass_sels),
287 CLK_SET_RATE_PARENT));
288 clk_dm(IMX8MM_SYS_PLL3_BYPASS,
289 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
290 sys_pll3_bypass_sels,
291 ARRAY_SIZE(sys_pll3_bypass_sels),
292 CLK_SET_RATE_PARENT));
293
294 /* PLL out gate */
295 clk_dm(IMX8MM_DRAM_PLL_OUT,
296 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
297 base + 0x50, 13));
298 clk_dm(IMX8MM_ARM_PLL_OUT,
299 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
300 base + 0x84, 11));
301 clk_dm(IMX8MM_SYS_PLL1_OUT,
302 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
303 base + 0x94, 11));
304 clk_dm(IMX8MM_SYS_PLL2_OUT,
305 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
306 base + 0x104, 11));
307 clk_dm(IMX8MM_SYS_PLL3_OUT,
308 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
309 base + 0x114, 11));
310
311 /* SYS PLL fixed output */
312 clk_dm(IMX8MM_SYS_PLL1_40M,
313 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
314 clk_dm(IMX8MM_SYS_PLL1_80M,
315 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
316 clk_dm(IMX8MM_SYS_PLL1_100M,
317 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
318 clk_dm(IMX8MM_SYS_PLL1_133M,
319 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
320 clk_dm(IMX8MM_SYS_PLL1_160M,
321 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
322 clk_dm(IMX8MM_SYS_PLL1_200M,
323 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
324 clk_dm(IMX8MM_SYS_PLL1_266M,
325 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
326 clk_dm(IMX8MM_SYS_PLL1_400M,
327 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
328 clk_dm(IMX8MM_SYS_PLL1_800M,
329 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
330
331 clk_dm(IMX8MM_SYS_PLL2_50M,
332 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
333 clk_dm(IMX8MM_SYS_PLL2_100M,
334 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
335 clk_dm(IMX8MM_SYS_PLL2_125M,
336 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
337 clk_dm(IMX8MM_SYS_PLL2_166M,
338 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
339 clk_dm(IMX8MM_SYS_PLL2_200M,
340 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
341 clk_dm(IMX8MM_SYS_PLL2_250M,
342 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
343 clk_dm(IMX8MM_SYS_PLL2_333M,
344 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
345 clk_dm(IMX8MM_SYS_PLL2_500M,
346 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
347 clk_dm(IMX8MM_SYS_PLL2_1000M,
348 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
349
350 base = dev_read_addr_ptr(dev);
Sean Andersonb58106d2019-12-24 23:57:47 -0500351 if (!base)
Peng Fan525c8762019-08-19 07:54:04 +0000352 return -EINVAL;
353
354 clk_dm(IMX8MM_CLK_A53_SRC,
355 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
356 imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
357 clk_dm(IMX8MM_CLK_A53_CG,
358 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
359 clk_dm(IMX8MM_CLK_A53_DIV,
360 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
361 base + 0x8000, 0, 3));
362
363 clk_dm(IMX8MM_CLK_AHB,
364 imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
365 base + 0x9000));
366 clk_dm(IMX8MM_CLK_IPG_ROOT,
367 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
368
369 clk_dm(IMX8MM_CLK_ENET_AXI,
370 imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
371 base + 0x8880));
372 clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
373 imx8m_clk_composite_critical("nand_usdhc_bus",
374 imx8mm_nand_usdhc_sels,
375 base + 0x8900));
Ye Li0321edb2020-04-19 02:22:09 -0700376 clk_dm(IMX8MM_CLK_USB_BUS,
377 imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
Peng Fan525c8762019-08-19 07:54:04 +0000378
379 /* IP */
380 clk_dm(IMX8MM_CLK_USDHC1,
381 imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
382 base + 0xac00));
383 clk_dm(IMX8MM_CLK_USDHC2,
384 imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
385 base + 0xac80));
386 clk_dm(IMX8MM_CLK_I2C1,
387 imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
388 clk_dm(IMX8MM_CLK_I2C2,
389 imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
390 clk_dm(IMX8MM_CLK_I2C3,
391 imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
392 clk_dm(IMX8MM_CLK_I2C4,
393 imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
394 clk_dm(IMX8MM_CLK_WDOG,
395 imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
396 clk_dm(IMX8MM_CLK_USDHC3,
397 imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
398 base + 0xbc80));
Peng Fan2dff8792020-06-27 15:49:28 +0800399 clk_dm(IMX8MM_CLK_QSPI,
400 imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
Ye Li0321edb2020-04-19 02:22:09 -0700401 clk_dm(IMX8MM_CLK_USB_CORE_REF,
402 imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
403 clk_dm(IMX8MM_CLK_USB_PHY_REF,
404 imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
Frieder Schrempf339beba2021-06-07 14:36:43 +0200405 clk_dm(IMX8MM_CLK_ECSPI1,
406 imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
407 clk_dm(IMX8MM_CLK_ECSPI2,
408 imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
409 clk_dm(IMX8MM_CLK_ECSPI3,
410 imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
Peng Fan525c8762019-08-19 07:54:04 +0000411
Frieder Schrempf339beba2021-06-07 14:36:43 +0200412 clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
413 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
414 clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
415 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
416 clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
417 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
Peng Fan525c8762019-08-19 07:54:04 +0000418 clk_dm(IMX8MM_CLK_I2C1_ROOT,
419 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
420 clk_dm(IMX8MM_CLK_I2C2_ROOT,
421 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
422 clk_dm(IMX8MM_CLK_I2C3_ROOT,
423 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
424 clk_dm(IMX8MM_CLK_I2C4_ROOT,
425 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
426 clk_dm(IMX8MM_CLK_OCOTP_ROOT,
427 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
428 clk_dm(IMX8MM_CLK_USDHC1_ROOT,
429 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
430 clk_dm(IMX8MM_CLK_USDHC2_ROOT,
431 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
432 clk_dm(IMX8MM_CLK_WDOG1_ROOT,
433 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
434 clk_dm(IMX8MM_CLK_WDOG2_ROOT,
435 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
436 clk_dm(IMX8MM_CLK_WDOG3_ROOT,
437 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
438 clk_dm(IMX8MM_CLK_USDHC3_ROOT,
439 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
Peng Fan2dff8792020-06-27 15:49:28 +0800440 clk_dm(IMX8MM_CLK_QSPI_ROOT,
441 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
Ye Li0321edb2020-04-19 02:22:09 -0700442 clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
443 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
Peng Fan525c8762019-08-19 07:54:04 +0000444
Peng Fanee5515d2019-10-22 03:29:48 +0000445 /* clks not needed in SPL stage */
446#ifndef CONFIG_SPL_BUILD
447 clk_dm(IMX8MM_CLK_ENET_REF,
448 imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
449 base + 0xa980));
450 clk_dm(IMX8MM_CLK_ENET_TIMER,
451 imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
452 base + 0xaa00));
453 clk_dm(IMX8MM_CLK_ENET_PHY_REF,
454 imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
455 base + 0xaa80));
456 clk_dm(IMX8MM_CLK_ENET1_ROOT,
457 imx_clk_gate4("enet1_root_clk", "enet_axi",
458 base + 0x40a0, 0));
459#endif
460
Peng Fan525c8762019-08-19 07:54:04 +0000461 return 0;
462}
463
464static const struct udevice_id imx8mm_clk_ids[] = {
465 { .compatible = "fsl,imx8mm-ccm" },
466 { },
467};
468
469U_BOOT_DRIVER(imx8mm_clk) = {
470 .name = "clk_imx8mm",
471 .id = UCLASS_CLK,
472 .of_match = imx8mm_clk_ids,
473 .ops = &imx8mm_clk_ops,
474 .probe = imx8mm_clk_probe,
475 .flags = DM_FLAG_PRE_RELOC,
476};