| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * DMA Engine. |
| 2 | |
| 3 | The Octeon DMA Engine transfers between the Boot Bus and main memory. |
| 4 | The DMA Engine will be referred to by phandle by any device that is |
| 5 | connected to it. |
| 6 | |
| 7 | Properties: |
| 8 | - compatible: "cavium,octeon-5750-bootbus-dma" |
| 9 | |
| 10 | Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. |
| 11 | |
| 12 | - reg: The base address of the DMA Engine's register bank. |
| 13 | |
| 14 | - interrupts: A single interrupt specifier. |
| 15 | |
| 16 | Example: |
| 17 | dma0: dma-engine@1180000000100 { |
| 18 | compatible = "cavium,octeon-5750-bootbus-dma"; |
| 19 | reg = <0x11800 0x00000100 0x0 0x8>; |
| 20 | interrupts = <0 63>; |
| 21 | }; |