Blame - drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h - filogic/uboot

Dave Gerlach

2c861a9

2021-05-11 10:22:12 -0500

[diff] [blame]

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/* SPDX-License-Identifier: BSD-3-Clause */

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/*

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* Cadence DDR Driver

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*

Bryan Brattlof

85b5cc8

2022-10-24 16:53:28 -0500

[diff] [blame]

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Dave Gerlach

2c861a9

2021-05-11 10:22:12 -0500

[diff] [blame]

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*/

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#ifndef REG_LPDDR4_PI_MACROS_H_

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#define REG_LPDDR4_PI_MACROS_H_

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#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U

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#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U

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#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U

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#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U

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#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U

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#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U

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#define LPDDR4__PI_START__REG DENALI_PI_0

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#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U

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#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0

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#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS

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#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U

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#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1

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#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0

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#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U

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#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2

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#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1

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#define LPDDR4__DENALI_PI_3_READ_MASK 0x0101FFFFU

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#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0101FFFFU

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#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU

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#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U

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#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U

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#define LPDDR4__PI_ID__REG DENALI_PI_3

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#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT 16U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH 1U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR 0U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET 0U

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#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3

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#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT 24U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH 1U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR 0U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET 0U

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#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3

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#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ

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#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFF0301U

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#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFF0301U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT 0U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH 1U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR 0U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET 0U

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#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4

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#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN

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#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK 0x00000300U

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#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT 8U

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#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH 2U

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#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4

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#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD

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#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK 0xFFFF0000U

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#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT 16U

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#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH 16U

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#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4

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#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP

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#define LPDDR4__DENALI_PI_5_READ_MASK 0x030100FFU

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#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x030100FFU

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#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK 0x000000FFU

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#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT 0U

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#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH 8U

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#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5

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#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT 8U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U

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#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5

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#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT 16U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET 0U

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#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5

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#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION

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#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK 0x03000000U

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#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT 24U

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#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH 2U

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#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5

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#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE

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#define LPDDR4__DENALI_PI_6_READ_MASK 0x00000101U

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#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00000101U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 0U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U

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#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6

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#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 8U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U

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#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6

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#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R

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#define LPDDR4__DENALI_PI_7_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_7_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT 0U

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#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH 32U

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#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7

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#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX

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#define LPDDR4__DENALI_PI_8_READ_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_8_WRITE_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT 0U

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH 20U

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#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8

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#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP

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#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT 0U

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH 20U

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#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9

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#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP

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#define LPDDR4__DENALI_PI_10_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_10_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT 0U

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH 32U

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#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10

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#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX

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#define LPDDR4__DENALI_PI_11_READ_MASK 0x0000011FU

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#define LPDDR4__DENALI_PI_11_WRITE_MASK 0x0000011FU

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#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK 0x0000001FU

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#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT 0U

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#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH 5U

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#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11

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#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET 0U

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#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11

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#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY

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#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U

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#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12

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#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP

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#define LPDDR4__DENALI_PI_13_READ_MASK 0x01030101U

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#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x01030101U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 0U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U

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#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13

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#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 8U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U

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#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13

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#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1

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#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK 0x00030000U

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#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT 16U

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#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH 2U

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#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13

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#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT 24U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET 0U

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#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13

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#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL

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#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F03U

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#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F03U

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#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK 0x00000003U

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#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT 0U

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#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH 2U

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#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14

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#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U

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#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14

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#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U

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#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14

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#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN

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#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U

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#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U

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#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U

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#define LPDDR4__PI_TMRR__REG DENALI_PI_14

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#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR

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#define LPDDR4__DENALI_PI_15_READ_MASK 0x0101070FU

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#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x0101070FU

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#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK 0x0000000FU

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#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT 0U

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#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH 4U

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#define LPDDR4__PI_TMPRR__REG DENALI_PI_15

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#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR

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#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK 0x00000700U

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#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT 8U

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#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH 3U

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#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15

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#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 16U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U

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#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15

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#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 24U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U

281

#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15

282

#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2

283

284

#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU

285

#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU

286

#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU

287

#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U

288

#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U

289

#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16

290

#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL

291

292

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U

293

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U

294

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U

295

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U

296

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U

297

#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16

298

#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS

299

300

#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U

301

#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U

302

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U

303

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U

304

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U

305

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U

306

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U

307

#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17

308

#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION

309

310

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U

311

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U

312

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U

313

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U

314

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U

315

#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17

316

#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD

317

318

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U

319

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U

320

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U

321

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U

322

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U

323

#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17

324

#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE

325

326

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U

327

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U

328

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U

329

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U

330

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U

331

#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17

332

#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0

333

334

#define LPDDR4__DENALI_PI_18_READ_MASK 0x03030301U

335

#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03030301U

336

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U

337

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U

338

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U

339

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U

340

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U

341

#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18

342

#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1

343

344

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x00000300U

345

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 8U

346

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U

347

#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18

348

#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0

349

350

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_MASK 0x00030000U

351

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_SHIFT 16U

352

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_WIDTH 2U

353

#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_18

354

#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1

355

356

#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_MASK 0x03000000U

357

#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_SHIFT 24U

358

#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_WIDTH 2U

359

#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_18

360

#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0

361

362

#define LPDDR4__DENALI_PI_19_READ_MASK 0x00000007U

363

#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x00000007U

364

#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_MASK 0x00000007U

365

#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_SHIFT 0U

366

#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_WIDTH 3U

367

#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_19

368

#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE

369

370

#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_MASK 0x00000100U

371

#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_SHIFT 8U

372

#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WIDTH 1U

373

#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOCLR 0U

374

#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOSET 0U

375

#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_19

376

#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_START

377

378

#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_MASK 0x00010000U

379

#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_SHIFT 16U

380

#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WIDTH 1U

381

#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOCLR 0U

382

#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOSET 0U

383

#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_19

384

#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT

385

386

#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U

387

#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_SHIFT 24U

388

#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WIDTH 1U

389

#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOCLR 0U

390

#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOSET 0U

391

#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_19

392

#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0

393

394

#define LPDDR4__DENALI_PI_20_READ_MASK 0x00030000U

395

#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00030000U

396

#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U

397

#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_SHIFT 0U

398

#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WIDTH 1U

399

#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOCLR 0U

400

#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOSET 0U

401

#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_20

402

#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0

403

404

#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U

405

#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U

406

#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U

407

#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U

408

#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U

409

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_20

410

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0

411

412

#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U

413

#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_SHIFT 16U

414

#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_WIDTH 2U

415

#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_20

416

#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0

417

418

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U

419

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_SHIFT 24U

420

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WIDTH 1U

421

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOCLR 0U

422

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOSET 0U

423

#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_20

424

#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1

425

426

#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U

427

#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U

428

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U

429

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_SHIFT 0U

430

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WIDTH 1U

431

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOCLR 0U

432

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOSET 0U

433

#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_21

434

#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1

435

436

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U

437

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U

438

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U

439

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U

440

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U

441

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_21

442

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1

443

444

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U

445

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_SHIFT 16U

446

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_WIDTH 2U

447

#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_21

448

#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1

449

450

#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_MASK 0x01000000U

451

#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_SHIFT 24U

452

#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WIDTH 1U

453

#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOCLR 0U

454

#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOSET 0U

455

#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_21

456

#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START

457

458

#define LPDDR4__DENALI_PI_22_READ_MASK 0x01000000U

459

#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x01000000U

460

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_MASK 0x00000001U

461

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_SHIFT 0U

462

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WIDTH 1U

463

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOCLR 0U

464

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOSET 0U

465

#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_22

466

#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR

467

468

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_MASK 0x00000100U

469

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_SHIFT 8U

470

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WIDTH 1U

471

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOCLR 0U

472

#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOSET 0U

473

#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_22

474

#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD

475

476

#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U

477

#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U

478

#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U

479

#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U

480

#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOSET 0U

481

#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_22

482

#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ

483

484

#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_MASK 0x01000000U

485

#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_SHIFT 24U

486

#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WIDTH 1U

487

#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOCLR 0U

488

#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOSET 0U

489

#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_22

490

#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN

491

492

#define LPDDR4__DENALI_PI_23_READ_MASK 0x00010101U

493

#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00010101U

494

#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_MASK 0x00000001U

495

#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_SHIFT 0U

496

#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WIDTH 1U

497

#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOCLR 0U

498

#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOSET 0U

499

#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_23

500

#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN

501

502

#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_MASK 0x00000100U

503

#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_SHIFT 8U

504

#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WIDTH 1U

505

#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOCLR 0U

506

#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOSET 0U

507

#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_23

508

#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN

509

510

#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_MASK 0x00010000U

511

#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_SHIFT 16U

512

#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WIDTH 1U

513

#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOCLR 0U

514

#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOSET 0U

515

#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_23

516

#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY

517

518

#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_MASK 0x01000000U

519

#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_SHIFT 24U

520

#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WIDTH 1U

521

#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOCLR 0U

522

#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOSET 0U

523

#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_23

524

#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_23__PI_WRLVL_REQ

525

526

#define LPDDR4__DENALI_PI_24_READ_MASK 0x3F3F0103U

527

#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x3F3F0103U

528

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_MASK 0x00000003U

529

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_SHIFT 0U

530

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_WIDTH 2U

531

#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_24

532

#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW

533

534

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_MASK 0x00000100U

535

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SHIFT 8U

536

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WIDTH 1U

537

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOCLR 0U

538

#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOSET 0U

539

#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_24

540

#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS

541

542

#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_MASK 0x003F0000U

543

#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_SHIFT 16U

544

#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_WIDTH 6U

545

#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_24

546

#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_24__PI_WLDQSEN

547

548

#define LPDDR4__DENALI_PI_24__PI_WLMRD_MASK 0x3F000000U

549

#define LPDDR4__DENALI_PI_24__PI_WLMRD_SHIFT 24U

550

#define LPDDR4__DENALI_PI_24__PI_WLMRD_WIDTH 6U

551

#define LPDDR4__PI_WLMRD__REG DENALI_PI_24

552

#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_24__PI_WLMRD

553

554

#define LPDDR4__DENALI_PI_25_READ_MASK 0x0101FFFFU

555

#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x0101FFFFU

556

#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU

557

#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_SHIFT 0U

558

#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_WIDTH 16U

559

#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_25

560

#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL

561

562

#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_MASK 0x00010000U

563

#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_SHIFT 16U

564

#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U

565

#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U

566

#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOSET 0U

567

#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_25

568

#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT

569

570

#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_MASK 0x01000000U

571

#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_SHIFT 24U

572

#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WIDTH 1U

573

#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOCLR 0U

574

#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOSET 0U

575

#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_25

576

#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS

577

578

#define LPDDR4__DENALI_PI_26_READ_MASK 0x01030103U

579

#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x01030103U

580

#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_MASK 0x00000003U

581

#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_SHIFT 0U

582

#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_WIDTH 2U

583

#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_26

584

#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK

585

586

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_MASK 0x00000100U

587

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_SHIFT 8U

588

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WIDTH 1U

589

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOCLR 0U

590

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOSET 0U

591

#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_26

592

#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE

593

594

#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_MASK 0x00030000U

595

#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_SHIFT 16U

596

#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_WIDTH 2U

597

#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_26

598

#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP

599

600

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_MASK 0x01000000U

601

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_SHIFT 24U

602

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WIDTH 1U

603

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOCLR 0U

604

#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOSET 0U

605

#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_26

606

#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT

607

608

#define LPDDR4__DENALI_PI_27_READ_MASK 0x0000FF01U

609

#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x0000FF01U

610

#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U

611

#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_SHIFT 0U

612

#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WIDTH 1U

613

#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOCLR 0U

614

#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOSET 0U

615

#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_27

616

#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS

617

618

#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U

619

#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_SHIFT 8U

620

#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_WIDTH 8U

621

#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_27

622

#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN

623

624

#define LPDDR4__DENALI_PI_28_READ_MASK 0xFFFFFFFFU

625

#define LPDDR4__DENALI_PI_28_WRITE_MASK 0xFFFFFFFFU

626

#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU

627

#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_SHIFT 0U

628

#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_WIDTH 32U

629

#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_28

630

#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP

631

632

#define LPDDR4__DENALI_PI_29_READ_MASK 0xFFFFFFFFU

633

#define LPDDR4__DENALI_PI_29_WRITE_MASK 0xFFFFFFFFU

634

#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU

635

#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_SHIFT 0U

636

#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_WIDTH 32U

637

#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_29

638

#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX

639

640

#define LPDDR4__DENALI_PI_30_READ_MASK 0x030F0F1FU

641

#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x030F0F1FU

642

#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU

643

#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_SHIFT 0U

644

#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_WIDTH 5U

645

#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_30

646

#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM

647

648

#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_MASK 0x00000F00U

649

#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_SHIFT 8U

650

#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_WIDTH 4U

651

#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_30

652

#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_30__PI_TODTH_WR

653

654

#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_MASK 0x000F0000U

655

#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_SHIFT 16U

656

#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_WIDTH 4U

657

#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_30

658

#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_30__PI_TODTH_RD

659

660

#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_MASK 0x03000000U

661

#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_SHIFT 24U

662

#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_WIDTH 2U

663

#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_30

664

#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_30__PI_ODT_VALUE

665

666

#define LPDDR4__DENALI_PI_31_READ_MASK 0x00000003U

667

#define LPDDR4__DENALI_PI_31_WRITE_MASK 0x00000003U

668

#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_MASK 0x00000003U

669

#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_SHIFT 0U

670

#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_WIDTH 2U

671

#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_31

672

#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING

673

674

#define LPDDR4__DENALI_PI_32_READ_MASK 0x03FFFFFFU

675

#define LPDDR4__DENALI_PI_32_WRITE_MASK 0x03FFFFFFU

676

#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU

677

#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_SHIFT 0U

678

#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_WIDTH 26U

679

#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_32

680

#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT

681

682

#define LPDDR4__DENALI_PI_33_READ_MASK 0x00000F07U

683

#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x00000F07U

684

#define LPDDR4__DENALI_PI_33__PI_RESERVED3_MASK 0x00000007U

685

#define LPDDR4__DENALI_PI_33__PI_RESERVED3_SHIFT 0U

686

#define LPDDR4__DENALI_PI_33__PI_RESERVED3_WIDTH 3U

687

#define LPDDR4__PI_RESERVED3__REG DENALI_PI_33

688

#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_33__PI_RESERVED3

689

690

#define LPDDR4__DENALI_PI_33__PI_RESERVED4_MASK 0x00000F00U

691

#define LPDDR4__DENALI_PI_33__PI_RESERVED4_SHIFT 8U

692

#define LPDDR4__DENALI_PI_33__PI_RESERVED4_WIDTH 4U

693

#define LPDDR4__PI_RESERVED4__REG DENALI_PI_33

694

#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_33__PI_RESERVED4

695

696

#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_MASK 0x00010000U

697

#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_SHIFT 16U

698

#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WIDTH 1U

699

#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOCLR 0U

700

#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOSET 0U

701

#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_33

702

#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_REQ

703

704

#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_MASK 0x01000000U

705

#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_SHIFT 24U

706

#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WIDTH 1U

707

#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOCLR 0U

708

#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOSET 0U

709

#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_33

710

#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ

711

712

#define LPDDR4__DENALI_PI_34_READ_MASK 0x00000103U

713

#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00000103U

714

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_MASK 0x00000003U

715

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_SHIFT 0U

716

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_WIDTH 2U

717

#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_34

718

#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW

719

720

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00000100U

721

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 8U

722

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 1U

723

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOCLR 0U

724

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOSET 0U

725

#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34

726

#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS

727

728

#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU

729

#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU

730

#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU

731

#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U

732

#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U

733

#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35

734

#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0

735

736

#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU

737

#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU

738

#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU

739

#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U

740

#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U

741

#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36

742

#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1

743

744

#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU

745

#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU

746

#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU

747

#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U

748

#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U

749

#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37

750

#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2

751

752

#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU

753

#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU

754

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU

755

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U

756

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U

757

#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38

758

#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3

759

760

#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU

761

#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU

762

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU

763

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U

764

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U

765

#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39

766

#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4

767

768

#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU

769

#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU

770

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU

771

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U

772

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U

773

#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40

774

#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5

775

776

#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU

777

#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU

778

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU

779

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U

780

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U

781

#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41

782

#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6

783

784

#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU

785

#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU

786

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU

787

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U

788

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U

789

#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42

790

#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7

791

792

#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU

793

#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU

794

#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU

795

#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U

796

#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U

797

#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43

798

#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN

799

800

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00000100U

801

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 8U

802

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U

803

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U

804

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U

805

#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43

806

#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT

807

808

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x00010000U

809

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 16U

810

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U

811

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U

812

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U

813

#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43

814

#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS

815

816

#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x01000000U

817

#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 24U

818

#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U

819

#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U

820

#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U

821

#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_43

822

#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT

823

824

#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U

825

#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U

826

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00000001U

827

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 0U

828

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U

829

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U

830

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U

831

#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44

832

#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS

833

834

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_MASK 0x00000100U

835

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_SHIFT 8U

836

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WIDTH 1U

837

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOCLR 0U

838

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOSET 0U

839

#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_44

840

#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT

841

842

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_MASK 0x00010000U

843

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT 16U

844

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH 1U

845

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR 0U

846

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET 0U

847

#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_44

848

#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT

849

850

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U

851

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U

852

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U

853

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U

854

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U

855

#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44

856

#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE

857

858

#define LPDDR4__DENALI_PI_45_READ_MASK 0x00030301U

859

#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x00030301U

860

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U

861

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U

862

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U

863

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U

864

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U

865

#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45

866

#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE

867

868

#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000300U

869

#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U

870

#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 2U

871

#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45

872

#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP

873

874

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x00030000U

875

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U

876

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 2U

877

#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45

878

#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP

879

880

#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU

881

#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU

882

#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU

883

#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U

884

#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U

885

#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46

886

#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR

887

888

#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU

889

#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU

890

#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU

891

#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U

892

#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U

893

#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47

894

#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP

895

896

#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF03U

897

#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF03U

898

#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x00000003U

899

#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U

900

#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 2U

901

#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48

902

#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK

903

904

#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U

905

#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U

906

#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U

907

#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48

908

#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN

909

910

#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU

911

#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU

912

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU

913

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U

914

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U

915

#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49

916

#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX

917

918

#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U

919

#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U

920

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U

921

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U

922

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U

923

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U

924

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U

925

#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50

926

#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS

927

928

#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U

929

#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U

930

#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U

931

#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50

932

#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL

933

934

#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU

935

#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU

936

#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU

937

#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U

938

#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U

939

#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51

940

#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL

941

942

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U

943

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U

944

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U

945

#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51

946

#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START

947

948

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U

949

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U

950

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U

951

#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51

952

#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM

953

954

#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU

955

#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU

956

#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU

957

#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U

958

#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U

959

#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52

960

#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM

961

962

#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U

963

#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U

964

#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U

965

#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52

966

#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM

967

968

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U

969

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U

970

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U

971

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U

972

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U

973

#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52

974

#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN

975

976

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U

977

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U

978

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U

979

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U

980

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U

981

#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52

982

#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE

983

984

#define LPDDR4__DENALI_PI_53_READ_MASK 0x0300FFFFU

985

#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x0300FFFFU

986

#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x000000FFU

987

#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U

988

#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 8U

989

#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53

990

#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN

991

992

#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x0000FF00U

993

#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U

994

#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 8U

995

#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53

996

#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT

997

998

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U

999

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U

1000

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U

1001

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U

1002

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U

1003

#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53

1004

#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ

1005

1006

#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_MASK 0x03000000U

1007

#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_SHIFT 24U

1008

#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_WIDTH 2U

1009

#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_53

1010

#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW

1011

1012

#define LPDDR4__DENALI_PI_54_READ_MASK 0x030F0101U

1013

#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x030F0101U

1014

#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_MASK 0x00000001U

1015

#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_SHIFT 0U

1016

#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WIDTH 1U

1017

#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOCLR 0U

1018

#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOSET 0U

1019

#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_54

1020

#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_54__PI_CALVL_CS

1021

1022

#define LPDDR4__DENALI_PI_54__PI_RESERVED5_MASK 0x00000100U

1023

#define LPDDR4__DENALI_PI_54__PI_RESERVED5_SHIFT 8U

1024

#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WIDTH 1U

1025

#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOCLR 0U

1026

#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOSET 0U

1027

#define LPDDR4__PI_RESERVED5__REG DENALI_PI_54

1028

#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_54__PI_RESERVED5

1029

1030

#define LPDDR4__DENALI_PI_54__PI_RESERVED6_MASK 0x000F0000U

1031

#define LPDDR4__DENALI_PI_54__PI_RESERVED6_SHIFT 16U

1032

#define LPDDR4__DENALI_PI_54__PI_RESERVED6_WIDTH 4U

1033

#define LPDDR4__PI_RESERVED6__REG DENALI_PI_54

1034

#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_54__PI_RESERVED6

1035

1036

#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x03000000U

1037

#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 24U

1038

#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U

1039

#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54

1040

#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN

1041

1042

#define LPDDR4__DENALI_PI_55_READ_MASK 0x01010101U

1043

#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x01010101U

1044

#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_MASK 0x00000001U

1045

#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_SHIFT 0U

1046

#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WIDTH 1U

1047

#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOCLR 0U

1048

#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOSET 0U

1049

#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_55

1050

#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC

1051

1052

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000100U

1053

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 8U

1054

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U

1055

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U

1056

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U

1057

#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55

1058

#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT

1059

1060

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00010000U

1061

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 16U

1062

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U

1063

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U

1064

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U

1065

#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55

1066

#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS

1067

1068

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x01000000U

1069

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 24U

1070

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U

1071

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U

1072

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U

1073

#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55

1074

#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE

1075

1076

#define LPDDR4__DENALI_PI_56_READ_MASK 0x0000FF03U

1077

#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x0000FF03U

1078

#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_MASK 0x00000003U

1079

#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_SHIFT 0U

1080

#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_WIDTH 2U

1081

#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_56

1082

#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP

1083

1084

#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x0000FF00U

1085

#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 8U

1086

#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U

1087

#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56

1088

#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN

1089

1090

#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU

1091

#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU

1092

#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU

1093

#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U

1094

#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U

1095

#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57

1096

#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP

1097

1098

#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU

1099

#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU

1100

#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU

1101

#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U

1102

#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U

1103

#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58

1104

#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX

1105

1106

#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U

1107

#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U

1108

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U

1109

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U

1110

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U

1111

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U

1112

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U

1113

#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59

1114

#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK

1115

1116

#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U

1117

#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U

1118

#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U

1119

#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59

1120

#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS

1121

1122

#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U

1123

#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U

1124

#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U

1125

#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59

1126

#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL

1127

1128

#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU

1129

#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU

1130

#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU

1131

#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U

1132

#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U

1133

#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60

1134

#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL

1135

1136

#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U

1137

#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U

1138

#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U

1139

#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60

1140

#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD

1141

1142

#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U

1143

#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U

1144

#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U

1145

#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60

1146

#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH

1147

1148

#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U

1149

#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U

1150

#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U

1151

#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60

1152

#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT

1153

1154

#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U

1155

#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U

1156

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U

1157

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U

1158

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U

1159

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U

1160

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U

1161

#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61

1162

#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN

1163

1164

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U

1165

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U

1166

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U

1167

#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61

1168

#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE

1169

1170

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U

1171

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U

1172

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U

1173

#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61

1174

#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE

1175

1176

#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U

1177

#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U

1178

#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U

1179

#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61

1180

#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN

1181

1182

#define LPDDR4__DENALI_PI_62_READ_MASK 0x017F1FFFU

1183

#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x017F1FFFU

1184

#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x000000FFU

1185

#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 0U

1186

#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 8U

1187

#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62

1188

#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH

1189

1190

#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x00001F00U

1191

#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 8U

1192

#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U

1193

#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62

1194

#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM

1195

1196

#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x007F0000U

1197

#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 16U

1198

#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U

1199

#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62

1200

#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF

1201

1202

#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U

1203

#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U

1204

#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U

1205

#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U

1206

#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U

1207

#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_62

1208

#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE

1209

1210

#define LPDDR4__DENALI_PI_63_READ_MASK 0xFF01FFFFU

1211

#define LPDDR4__DENALI_PI_63_WRITE_MASK 0xFF01FFFFU

1212

#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU

1213

#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U

1214

#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U

1215

#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63

1216

#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START

1217

1218

#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U

1219

#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U

1220

#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U

1221

#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63

1222

#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE

1223

1224

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U

1225

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U

1226

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U

1227

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U

1228

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U

1229

#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63

1230

#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL

1231

1232

#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_MASK 0xFF000000U

1233

#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 24U

1234

#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U

1235

#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_63

1236

#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN

1237

1238

#define LPDDR4__DENALI_PI_64_READ_MASK 0x01010101U

1239

#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x01010101U

1240

#define LPDDR4__DENALI_PI_64__PI_VREF_CS_MASK 0x00000001U

1241

#define LPDDR4__DENALI_PI_64__PI_VREF_CS_SHIFT 0U

1242

#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WIDTH 1U

1243

#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOCLR 0U

1244

#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOSET 0U

1245

#define LPDDR4__PI_VREF_CS__REG DENALI_PI_64

1246

#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_64__PI_VREF_CS

1247

1248

#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_MASK 0x00000100U

1249

#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_SHIFT 8U

1250

#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WIDTH 1U

1251

#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOCLR 0U

1252

#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOSET 0U

1253

#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_64

1254

#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN

1255

1256

#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_MASK 0x00010000U

1257

#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_SHIFT 16U

1258

#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WIDTH 1U

1259

#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOCLR 0U

1260

#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOSET 0U

1261

#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_64

1262

#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS

1263

1264

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x01000000U

1265

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 24U

1266

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U

1267

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U

1268

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U

1269

#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64

1270

#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE

1271

1272

#define LPDDR4__DENALI_PI_65_READ_MASK 0x030701FFU

1273

#define LPDDR4__DENALI_PI_65_WRITE_MASK 0x030701FFU

1274

#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU

1275

#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT 0U

1276

#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH 8U

1277

#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_65

1278

#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT

1279

1280

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_MASK 0x00000100U

1281

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_SHIFT 8U

1282

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WIDTH 1U

1283

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOCLR 0U

1284

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOSET 0U

1285

#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_65

1286

#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN

1287

1288

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_MASK 0x00070000U

1289

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_SHIFT 16U

1290

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_WIDTH 3U

1291

#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_65

1292

#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM

1293

1294

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_MASK 0x03000000U

1295

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_SHIFT 24U

1296

#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_WIDTH 2U

1297

#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_65

1298

#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK

1299

1300

#define LPDDR4__DENALI_PI_66_READ_MASK 0x1F1F0301U

1301

#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x1F1F0301U

1302

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x00000001U

1303

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 0U

1304

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U

1305

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U

1306

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U

1307

#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66

1308

#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE

1309

1310

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_MASK 0x00000300U

1311

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_SHIFT 8U

1312

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_WIDTH 2U

1313

#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_66

1314

#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP

1315

1316

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x001F0000U

1317

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 16U

1318

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U

1319

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_66

1320

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE

1321

1322

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x1F000000U

1323

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 24U

1324

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U

1325

#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_66

1326

#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE

1327

1328

#define LPDDR4__DENALI_PI_67_READ_MASK 0x01030001U

1329

#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x01030001U

1330

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x00000001U

1331

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 0U

1332

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U

1333

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U

1334

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U

1335

#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67

1336

#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC

1337

1338

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_MASK 0x00000100U

1339

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_SHIFT 8U

1340

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WIDTH 1U

1341

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOCLR 0U

1342

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOSET 0U

1343

#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_67

1344

#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ

1345

1346

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_MASK 0x00030000U

1347

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_SHIFT 16U

1348

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_WIDTH 2U

1349

#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_67

1350

#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW

1351

1352

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MASK 0x01000000U

1353

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SHIFT 24U

1354

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WIDTH 1U

1355

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOCLR 0U

1356

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOSET 0U

1357

#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_67

1358

#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS

1359

1360

#define LPDDR4__DENALI_PI_68_READ_MASK 0x000000FFU

1361

#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x000000FFU

1362

#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x000000FFU

1363

#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 0U

1364

#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U

1365

#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68

1366

#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN

1367

1368

#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU

1369

#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU

1370

#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU

1371

#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U

1372

#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U

1373

#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69

1374

#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP

1375

1376

#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU

1377

#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU

1378

#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU

1379

#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U

1380

#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U

1381

#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70

1382

#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX

1383

1384

#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU

1385

#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU

1386

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU

1387

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U

1388

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U

1389

#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71

1390

#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL

1391

1392

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U

1393

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U

1394

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U

1395

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U

1396

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U

1397

#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71

1398

#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT

1399

1400

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_MASK 0x01000000U

1401

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_SHIFT 24U

1402

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WIDTH 1U

1403

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOCLR 0U

1404

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOSET 0U

1405

#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_71

1406

#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT

1407

1408

#define LPDDR4__DENALI_PI_72_READ_MASK 0x00030301U

1409

#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x00030301U

1410

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_MASK 0x00000001U

1411

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_SHIFT 0U

1412

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WIDTH 1U

1413

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOCLR 0U

1414

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOSET 0U

1415

#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_72

1416

#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS

1417

1418

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000300U

1419

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 8U

1420

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U

1421

#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72

1422

#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS

1423

1424

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_MASK 0x00030000U

1425

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT 16U

1426

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH 2U

1427

#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_72

1428

#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE

1429

1430

#define LPDDR4__DENALI_PI_73_READ_MASK 0xFFFFFFFFU

1431

#define LPDDR4__DENALI_PI_73_WRITE_MASK 0xFFFFFFFFU

1432

#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK 0xFFFFFFFFU

1433

#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT 0U

1434

#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH 32U

1435

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_73

1436

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0

1437

1438

#define LPDDR4__DENALI_PI_74_READ_MASK 0x00010101U

1439

#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x00010101U

1440

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK 0x00000001U

1441

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT 0U

1442

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH 1U

1443

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOCLR 0U

1444

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOSET 0U

1445

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_74

1446

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1

1447

1448

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_MASK 0x00000100U

1449

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_SHIFT 8U

1450

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WIDTH 1U

1451

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOCLR 0U

1452

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOSET 0U

1453

#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_74

1454

#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN

1455

1456

#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_MASK 0x00010000U

1457

#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_SHIFT 16U

1458

#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WIDTH 1U

1459

#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOCLR 0U

1460

#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOSET 0U

1461

#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_74

1462

#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM

1463

1464

#define LPDDR4__DENALI_PI_75_READ_MASK 0x010003FFU

1465

#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x010003FFU

1466

#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_MASK 0x000003FFU

1467

#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_SHIFT 0U

1468

#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_WIDTH 10U

1469

#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_75

1470

#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW

1471

1472

#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_MASK 0x00010000U

1473

#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT 16U

1474

#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH 1U

1475

#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR 0U

1476

#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET 0U

1477

#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_75

1478

#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START

1479

1480

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_MASK 0x01000000U

1481

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_SHIFT 24U

1482

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WIDTH 1U

1483

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOCLR 0U

1484

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOSET 0U

1485

#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_75

1486

#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE

1487

1488

#define LPDDR4__DENALI_PI_76_READ_MASK 0x01010101U

1489

#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x01010101U

1490

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_MASK 0x00000001U

1491

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_SHIFT 0U

1492

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WIDTH 1U

1493

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOCLR 0U

1494

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOSET 0U

1495

#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_76

1496

#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN

1497

1498

#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_MASK 0x00000100U

1499

#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_SHIFT 8U

1500

#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WIDTH 1U

1501

#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOCLR 0U

1502

#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOSET 0U

1503

#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_76

1504

#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN

1505

1506

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_MASK 0x00010000U

1507

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_SHIFT 16U

1508

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WIDTH 1U

1509

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOCLR 0U

1510

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOSET 0U

1511

#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_76

1512

#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN

1513

1514

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_MASK 0x01000000U

1515

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT 24U

1516

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH 1U

1517

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR 0U

1518

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOSET 0U

1519

#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_76

1520

#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN

1521

1522

#define LPDDR4__DENALI_PI_77_READ_MASK 0x1F070303U

1523

#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x1F070303U

1524

#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_MASK 0x00000003U

1525

#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_SHIFT 0U

1526

#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_WIDTH 2U

1527

#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_77

1528

#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK

1529

1530

#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_MASK 0x00000300U

1531

#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_SHIFT 8U

1532

#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_WIDTH 2U

1533

#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_77

1534

#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_77__PI_BANK_DIFF

1535

1536

#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_MASK 0x00070000U

1537

#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_SHIFT 16U

1538

#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_WIDTH 3U

1539

#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_77

1540

#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_77__PI_ROW_DIFF

1541

1542

#define LPDDR4__DENALI_PI_77__PI_TCCD_MASK 0x1F000000U

1543

#define LPDDR4__DENALI_PI_77__PI_TCCD_SHIFT 24U

1544

#define LPDDR4__DENALI_PI_77__PI_TCCD_WIDTH 5U

1545

#define LPDDR4__PI_TCCD__REG DENALI_PI_77

1546

#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_77__PI_TCCD

1547

1548

#define LPDDR4__DENALI_PI_78_READ_MASK 0x0F0F0F0FU

1549

#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x0F0F0F0FU

1550

#define LPDDR4__DENALI_PI_78__PI_RESERVED7_MASK 0x0000000FU

1551

#define LPDDR4__DENALI_PI_78__PI_RESERVED7_SHIFT 0U

1552

#define LPDDR4__DENALI_PI_78__PI_RESERVED7_WIDTH 4U

1553

#define LPDDR4__PI_RESERVED7__REG DENALI_PI_78

1554

#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_78__PI_RESERVED7

1555

1556

#define LPDDR4__DENALI_PI_78__PI_RESERVED8_MASK 0x00000F00U

1557

#define LPDDR4__DENALI_PI_78__PI_RESERVED8_SHIFT 8U

1558

#define LPDDR4__DENALI_PI_78__PI_RESERVED8_WIDTH 4U

1559

#define LPDDR4__PI_RESERVED8__REG DENALI_PI_78

1560

#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_78__PI_RESERVED8

1561

1562

#define LPDDR4__DENALI_PI_78__PI_RESERVED9_MASK 0x000F0000U

1563

#define LPDDR4__DENALI_PI_78__PI_RESERVED9_SHIFT 16U

1564

#define LPDDR4__DENALI_PI_78__PI_RESERVED9_WIDTH 4U

1565

#define LPDDR4__PI_RESERVED9__REG DENALI_PI_78

1566

#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_78__PI_RESERVED9

1567

1568

#define LPDDR4__DENALI_PI_78__PI_RESERVED10_MASK 0x0F000000U

1569

#define LPDDR4__DENALI_PI_78__PI_RESERVED10_SHIFT 24U

1570

#define LPDDR4__DENALI_PI_78__PI_RESERVED10_WIDTH 4U

1571

#define LPDDR4__PI_RESERVED10__REG DENALI_PI_78

1572

#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_78__PI_RESERVED10

1573

1574

#define LPDDR4__DENALI_PI_79_READ_MASK 0x0F0F0F0FU

1575

#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0F0F0F0FU

1576

#define LPDDR4__DENALI_PI_79__PI_RESERVED11_MASK 0x0000000FU

1577

#define LPDDR4__DENALI_PI_79__PI_RESERVED11_SHIFT 0U

1578

#define LPDDR4__DENALI_PI_79__PI_RESERVED11_WIDTH 4U

1579

#define LPDDR4__PI_RESERVED11__REG DENALI_PI_79

1580

#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_79__PI_RESERVED11

1581

1582

#define LPDDR4__DENALI_PI_79__PI_RESERVED12_MASK 0x00000F00U

1583

#define LPDDR4__DENALI_PI_79__PI_RESERVED12_SHIFT 8U

1584

#define LPDDR4__DENALI_PI_79__PI_RESERVED12_WIDTH 4U

1585

#define LPDDR4__PI_RESERVED12__REG DENALI_PI_79

1586

#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_79__PI_RESERVED12

1587

1588

#define LPDDR4__DENALI_PI_79__PI_RESERVED13_MASK 0x000F0000U

1589

#define LPDDR4__DENALI_PI_79__PI_RESERVED13_SHIFT 16U

1590

#define LPDDR4__DENALI_PI_79__PI_RESERVED13_WIDTH 4U

1591

#define LPDDR4__PI_RESERVED13__REG DENALI_PI_79

1592

#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_79__PI_RESERVED13

1593

1594

#define LPDDR4__DENALI_PI_79__PI_RESERVED14_MASK 0x0F000000U

1595

#define LPDDR4__DENALI_PI_79__PI_RESERVED14_SHIFT 24U

1596

#define LPDDR4__DENALI_PI_79__PI_RESERVED14_WIDTH 4U

1597

#define LPDDR4__PI_RESERVED14__REG DENALI_PI_79

1598

#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_79__PI_RESERVED14

1599

1600

#define LPDDR4__DENALI_PI_80_READ_MASK 0x0F0F0F0FU

1601

#define LPDDR4__DENALI_PI_80_WRITE_MASK 0x0F0F0F0FU

1602

#define LPDDR4__DENALI_PI_80__PI_RESERVED15_MASK 0x0000000FU

1603

#define LPDDR4__DENALI_PI_80__PI_RESERVED15_SHIFT 0U

1604

#define LPDDR4__DENALI_PI_80__PI_RESERVED15_WIDTH 4U

1605

#define LPDDR4__PI_RESERVED15__REG DENALI_PI_80

1606

#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_80__PI_RESERVED15

1607

1608

#define LPDDR4__DENALI_PI_80__PI_RESERVED16_MASK 0x00000F00U

1609

#define LPDDR4__DENALI_PI_80__PI_RESERVED16_SHIFT 8U

1610

#define LPDDR4__DENALI_PI_80__PI_RESERVED16_WIDTH 4U

1611

#define LPDDR4__PI_RESERVED16__REG DENALI_PI_80

1612

#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_80__PI_RESERVED16

1613

1614

#define LPDDR4__DENALI_PI_80__PI_RESERVED17_MASK 0x000F0000U

1615

#define LPDDR4__DENALI_PI_80__PI_RESERVED17_SHIFT 16U

1616

#define LPDDR4__DENALI_PI_80__PI_RESERVED17_WIDTH 4U

1617

#define LPDDR4__PI_RESERVED17__REG DENALI_PI_80

1618

#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_80__PI_RESERVED17

1619

1620

#define LPDDR4__DENALI_PI_80__PI_RESERVED18_MASK 0x0F000000U

1621

#define LPDDR4__DENALI_PI_80__PI_RESERVED18_SHIFT 24U

1622

#define LPDDR4__DENALI_PI_80__PI_RESERVED18_WIDTH 4U

1623

#define LPDDR4__PI_RESERVED18__REG DENALI_PI_80

1624

#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_80__PI_RESERVED18

1625

1626

#define LPDDR4__DENALI_PI_81_READ_MASK 0x0F0F0F0FU

1627

#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0F0F0F0FU

1628

#define LPDDR4__DENALI_PI_81__PI_RESERVED19_MASK 0x0000000FU

1629

#define LPDDR4__DENALI_PI_81__PI_RESERVED19_SHIFT 0U

1630

#define LPDDR4__DENALI_PI_81__PI_RESERVED19_WIDTH 4U

1631

#define LPDDR4__PI_RESERVED19__REG DENALI_PI_81

1632

#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_81__PI_RESERVED19

1633

1634

#define LPDDR4__DENALI_PI_81__PI_RESERVED20_MASK 0x00000F00U

1635

#define LPDDR4__DENALI_PI_81__PI_RESERVED20_SHIFT 8U

1636

#define LPDDR4__DENALI_PI_81__PI_RESERVED20_WIDTH 4U

1637

#define LPDDR4__PI_RESERVED20__REG DENALI_PI_81

1638

#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_81__PI_RESERVED20

1639

1640

#define LPDDR4__DENALI_PI_81__PI_RESERVED21_MASK 0x000F0000U

1641

#define LPDDR4__DENALI_PI_81__PI_RESERVED21_SHIFT 16U

1642

#define LPDDR4__DENALI_PI_81__PI_RESERVED21_WIDTH 4U

1643

#define LPDDR4__PI_RESERVED21__REG DENALI_PI_81

1644

#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_81__PI_RESERVED21

1645

1646

#define LPDDR4__DENALI_PI_81__PI_RESERVED22_MASK 0x0F000000U

1647

#define LPDDR4__DENALI_PI_81__PI_RESERVED22_SHIFT 24U

1648

#define LPDDR4__DENALI_PI_81__PI_RESERVED22_WIDTH 4U

1649

#define LPDDR4__PI_RESERVED22__REG DENALI_PI_81

1650

#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_81__PI_RESERVED22

1651

1652

#define LPDDR4__DENALI_PI_82_READ_MASK 0x0F0F0F0FU

1653

#define LPDDR4__DENALI_PI_82_WRITE_MASK 0x0F0F0F0FU

1654

#define LPDDR4__DENALI_PI_82__PI_RESERVED23_MASK 0x0000000FU

1655

#define LPDDR4__DENALI_PI_82__PI_RESERVED23_SHIFT 0U

1656

#define LPDDR4__DENALI_PI_82__PI_RESERVED23_WIDTH 4U

1657

#define LPDDR4__PI_RESERVED23__REG DENALI_PI_82

1658

#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_82__PI_RESERVED23

1659

1660

#define LPDDR4__DENALI_PI_82__PI_RESERVED24_MASK 0x00000F00U

1661

#define LPDDR4__DENALI_PI_82__PI_RESERVED24_SHIFT 8U

1662

#define LPDDR4__DENALI_PI_82__PI_RESERVED24_WIDTH 4U

1663

#define LPDDR4__PI_RESERVED24__REG DENALI_PI_82

1664

#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_82__PI_RESERVED24

1665

1666

#define LPDDR4__DENALI_PI_82__PI_RESERVED25_MASK 0x000F0000U

1667

#define LPDDR4__DENALI_PI_82__PI_RESERVED25_SHIFT 16U

1668

#define LPDDR4__DENALI_PI_82__PI_RESERVED25_WIDTH 4U

1669

#define LPDDR4__PI_RESERVED25__REG DENALI_PI_82

1670

#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_82__PI_RESERVED25

1671

1672

#define LPDDR4__DENALI_PI_82__PI_RESERVED26_MASK 0x0F000000U

1673

#define LPDDR4__DENALI_PI_82__PI_RESERVED26_SHIFT 24U

1674

#define LPDDR4__DENALI_PI_82__PI_RESERVED26_WIDTH 4U

1675

#define LPDDR4__PI_RESERVED26__REG DENALI_PI_82

1676

#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_82__PI_RESERVED26

1677

1678

#define LPDDR4__DENALI_PI_83_READ_MASK 0x3FFFFFFFU

1679

#define LPDDR4__DENALI_PI_83_WRITE_MASK 0x3FFFFFFFU

1680

#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_MASK 0x3FFFFFFFU

1681

#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_SHIFT 0U

1682

#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_WIDTH 30U

1683

#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_83

1684

#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_83__PI_INT_STATUS

1685

1686

#define LPDDR4__DENALI_PI_84__PI_INT_ACK_MASK 0x1FFFFFFFU

1687

#define LPDDR4__DENALI_PI_84__PI_INT_ACK_SHIFT 0U

1688

#define LPDDR4__DENALI_PI_84__PI_INT_ACK_WIDTH 29U

1689

#define LPDDR4__PI_INT_ACK__REG DENALI_PI_84

1690

#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_84__PI_INT_ACK

1691

1692

#define LPDDR4__DENALI_PI_85_READ_MASK 0x3FFFFFFFU

1693

#define LPDDR4__DENALI_PI_85_WRITE_MASK 0x3FFFFFFFU

1694

#define LPDDR4__DENALI_PI_85__PI_INT_MASK_MASK 0x3FFFFFFFU

1695

#define LPDDR4__DENALI_PI_85__PI_INT_MASK_SHIFT 0U

1696

#define LPDDR4__DENALI_PI_85__PI_INT_MASK_WIDTH 30U

1697

#define LPDDR4__PI_INT_MASK__REG DENALI_PI_85

1698

#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_85__PI_INT_MASK

1699

1700

#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU

1701

#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU

1702

#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU

1703

#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_SHIFT 0U

1704

#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_WIDTH 32U

1705

#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_86

1706

#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0

1707

1708

#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU

1709

#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU

1710

#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU

1711

#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_SHIFT 0U

1712

#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_WIDTH 32U

1713

#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_87

1714

#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1

1715

1716

#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU

1717

#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU

1718

#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU

1719

#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_SHIFT 0U

1720

#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_WIDTH 32U

1721

#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_88

1722

#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0

1723

1724

#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU

1725

#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU

1726

#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU

1727

#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_SHIFT 0U

1728

#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_WIDTH 32U

1729

#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_89

1730

#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1

1731

1732

#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU

1733

#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU

1734

#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU

1735

#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U

1736

#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U

1737

#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90

1738

#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0

1739

1740

#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F3F01U

1741

#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F3F01U

1742

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000001U

1743

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U

1744

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 1U

1745

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOCLR 0U

1746

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOSET 0U

1747

#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91

1748

#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1

1749

1750

#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00003F00U

1751

#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U

1752

#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 6U

1753

#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91

1754

#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN

1755

1756

#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U

1757

#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U

1758

#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U

1759

#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91

1760

#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK

1761

1762

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U

1763

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U

1764

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U

1765

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U

1766

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U

1767

#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91

1768

#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN

1769

1770

#define LPDDR4__DENALI_PI_92_READ_MASK 0x1F1F1F1FU

1771

#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x1F1F1F1FU

1772

#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_MASK 0x0000001FU

1773

#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_SHIFT 0U

1774

#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_WIDTH 5U

1775

#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_92

1776

#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX

1777

1778

#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_MASK 0x00001F00U

1779

#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_SHIFT 8U

1780

#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_WIDTH 5U

1781

#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_92

1782

#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_92__PI_ACT_N_MUX

1783

1784

#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_MASK 0x001F0000U

1785

#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_SHIFT 16U

1786

#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_WIDTH 5U

1787

#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_92

1788

#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_0

1789

1790

#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_MASK 0x1F000000U

1791

#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_SHIFT 24U

1792

#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_WIDTH 5U

1793

#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_92

1794

#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_1

1795

1796

#define LPDDR4__DENALI_PI_93_READ_MASK 0x1F1F1F1FU

1797

#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x1F1F1F1FU

1798

#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_MASK 0x0000001FU

1799

#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_SHIFT 0U

1800

#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_WIDTH 5U

1801

#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_93

1802

#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_RAS_N_MUX

1803

1804

#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_MASK 0x00001F00U

1805

#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_SHIFT 8U

1806

#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_WIDTH 5U

1807

#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_93

1808

#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_CAS_N_MUX

1809

1810

#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_MASK 0x001F0000U

1811

#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_SHIFT 16U

1812

#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_WIDTH 5U

1813

#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_93

1814

#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_WE_N_MUX

1815

1816

#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_MASK 0x1F000000U

1817

#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_SHIFT 24U

1818

#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_WIDTH 5U

1819

#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_93

1820

#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_93__PI_BANK_MUX_0

1821

1822

#define LPDDR4__DENALI_PI_94_READ_MASK 0x0101011FU

1823

#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x0101011FU

1824

#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_MASK 0x0000001FU

1825

#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_SHIFT 0U

1826

#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_WIDTH 5U

1827

#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_94

1828

#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_94__PI_BANK_MUX_1

1829

1830

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_MASK 0x00000100U

1831

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_SHIFT 8U

1832

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WIDTH 1U

1833

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOCLR 0U

1834

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOSET 0U

1835

#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_94

1836

#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN

1837

1838

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00010000U

1839

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 16U

1840

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 1U

1841

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOCLR 0U

1842

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOSET 0U

1843

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_94

1844

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0

1845

1846

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x01000000U

1847

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 24U

1848

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 1U

1849

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOCLR 0U

1850

#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOSET 0U

1851

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_94

1852

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1

1853

1854

#define LPDDR4__DENALI_PI_95_READ_MASK 0x03FFFF01U

1855

#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x03FFFF01U

1856

#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000001U

1857

#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 0U

1858

#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U

1859

#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U

1860

#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U

1861

#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_95

1862

#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN

1863

1864

#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_MASK 0x00FFFF00U

1865

#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_SHIFT 8U

1866

#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_WIDTH 16U

1867

#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_95

1868

#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN

1869

1870

#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U

1871

#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_SHIFT 24U

1872

#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_WIDTH 2U

1873

#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_95

1874

#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS

1875

1876

#define LPDDR4__DENALI_PI_96_READ_MASK 0x01030107U

1877

#define LPDDR4__DENALI_PI_96_WRITE_MASK 0x01030107U

1878

#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_MASK 0x00000007U

1879

#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_SHIFT 0U

1880

#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_WIDTH 3U

1881

#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_96

1882

#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT

1883

1884

#define LPDDR4__DENALI_PI_96__PI_BIST_GO_MASK 0x00000100U

1885

#define LPDDR4__DENALI_PI_96__PI_BIST_GO_SHIFT 8U

1886

#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WIDTH 1U

1887

#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOCLR 0U

1888

#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOSET 0U

1889

#define LPDDR4__PI_BIST_GO__REG DENALI_PI_96

1890

#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_96__PI_BIST_GO

1891

1892

#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_MASK 0x00030000U

1893

#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_SHIFT 16U

1894

#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_WIDTH 2U

1895

#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_96

1896

#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_96__PI_BIST_RESULT

1897

1898

#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_MASK 0x01000000U

1899

#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_SHIFT 24U

1900

#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WIDTH 1U

1901

#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOCLR 0U

1902

#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOSET 0U

1903

#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_96

1904

#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE

1905

1906

#define LPDDR4__DENALI_PI_97_READ_MASK 0x000101FFU

1907

#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x000101FFU

1908

#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_MASK 0x000000FFU

1909

#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_SHIFT 0U

1910

#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_WIDTH 8U

1911

#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_97

1912

#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_97__PI_ADDR_SPACE

1913

1914

#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_MASK 0x00000100U

1915

#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_SHIFT 8U

1916

#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WIDTH 1U

1917

#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOCLR 0U

1918

#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOSET 0U

1919

#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_97

1920

#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK

1921

1922

#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_MASK 0x00010000U

1923

#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_SHIFT 16U

1924

#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WIDTH 1U

1925

#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOCLR 0U

1926

#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOSET 0U

1927

#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_97

1928

#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK

1929

1930

#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU

1931

#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU

1932

#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU

1933

#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_SHIFT 0U

1934

#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_WIDTH 32U

1935

#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_98

1936

#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0

1937

1938

#define LPDDR4__DENALI_PI_99_READ_MASK 0x0000FF01U

1939

#define LPDDR4__DENALI_PI_99_WRITE_MASK 0x0000FF01U

1940

#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_MASK 0x00000001U

1941

#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_SHIFT 0U

1942

#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WIDTH 1U

1943

#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOCLR 0U

1944

#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOSET 0U

1945

#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_99

1946

#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1

1947

1948

#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U

1949

#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_SHIFT 8U

1950

#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_WIDTH 8U

1951

#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_99

1952

#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN

1953

1954

#define LPDDR4__DENALI_PI_100_READ_MASK 0xFFFFFFFFU

1955

#define LPDDR4__DENALI_PI_100_WRITE_MASK 0xFFFFFFFFU

1956

#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_MASK 0xFFFFFFFFU

1957

#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_SHIFT 0U

1958

#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_WIDTH 32U

1959

#define LPDDR4__PI_BIST_DATA_MASK__REG DENALI_PI_100

1960

#define LPDDR4__PI_BIST_DATA_MASK__FLD LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK

1961

1962

#define LPDDR4__DENALI_PI_101_READ_MASK 0x0FFF0FFFU

1963

#define LPDDR4__DENALI_PI_101_WRITE_MASK 0x0FFF0FFFU

1964

#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_MASK 0x00000FFFU

1965

#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_SHIFT 0U

1966

#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_WIDTH 12U

1967

#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_101

1968

#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT

1969

1970

#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_MASK 0x0FFF0000U

1971

#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_SHIFT 16U

1972

#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_WIDTH 12U

1973

#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_101

1974

#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP

1975

1976

#define LPDDR4__DENALI_PI_102_READ_MASK 0xFFFFFFFFU

1977

#define LPDDR4__DENALI_PI_102_WRITE_MASK 0xFFFFFFFFU

1978

#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU

1979

#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_SHIFT 0U

1980

#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_WIDTH 32U

1981

#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_102

1982

#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0

1983

1984

#define LPDDR4__DENALI_PI_103_READ_MASK 0x00000003U

1985

#define LPDDR4__DENALI_PI_103_WRITE_MASK 0x00000003U

1986

#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_MASK 0x00000003U

1987

#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_SHIFT 0U

1988

#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_WIDTH 2U

1989

#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_103

1990

#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1

1991

1992

#define LPDDR4__DENALI_PI_104_READ_MASK 0xFFFFFFFFU

1993

#define LPDDR4__DENALI_PI_104_WRITE_MASK 0xFFFFFFFFU

1994

#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU

1995

#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_SHIFT 0U

1996

#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_WIDTH 32U

1997

#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_104

1998

#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0

1999

2000

#define LPDDR4__DENALI_PI_105_READ_MASK 0x00000003U

2001

#define LPDDR4__DENALI_PI_105_WRITE_MASK 0x00000003U

2002

#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_MASK 0x00000003U

2003

#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_SHIFT 0U

2004

#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_WIDTH 2U

2005

#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_105

2006

#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1

2007

2008

#define LPDDR4__DENALI_PI_106_READ_MASK 0xFFFFFFFFU

2009

#define LPDDR4__DENALI_PI_106_WRITE_MASK 0xFFFFFFFFU

2010

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU

2011

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_SHIFT 0U

2012

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_WIDTH 32U

2013

#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_106

2014

#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0

2015

2016

#define LPDDR4__DENALI_PI_107_READ_MASK 0x00000003U

2017

#define LPDDR4__DENALI_PI_107_WRITE_MASK 0x00000003U

2018

#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_MASK 0x00000003U

2019

#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_SHIFT 0U

2020

#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_WIDTH 2U

2021

#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_107

2022

#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1

2023

2024

#define LPDDR4__DENALI_PI_108_READ_MASK 0xFFFFFFFFU

2025

#define LPDDR4__DENALI_PI_108_WRITE_MASK 0xFFFFFFFFU

2026

#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU

2027

#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_SHIFT 0U

2028

#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_WIDTH 32U

2029

#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_108

2030

#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0

2031

2032

#define LPDDR4__DENALI_PI_109_READ_MASK 0x00000003U

2033

#define LPDDR4__DENALI_PI_109_WRITE_MASK 0x00000003U

2034

#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_MASK 0x00000003U

2035

#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_SHIFT 0U

2036

#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_WIDTH 2U

2037

#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_109

2038

#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1

2039

2040

#define LPDDR4__DENALI_PI_110_READ_MASK 0xFFFFFFFFU

2041

#define LPDDR4__DENALI_PI_110_WRITE_MASK 0xFFFFFFFFU

2042

#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU

2043

#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_SHIFT 0U

2044

#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_WIDTH 32U

2045

#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_110

2046

#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0

2047

2048

#define LPDDR4__DENALI_PI_111_READ_MASK 0x00000003U

2049

#define LPDDR4__DENALI_PI_111_WRITE_MASK 0x00000003U

2050

#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_MASK 0x00000003U

2051

#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_SHIFT 0U

2052

#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_WIDTH 2U

2053

#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_111

2054

#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1

2055

2056

#define LPDDR4__DENALI_PI_112_READ_MASK 0xFFFFFFFFU

2057

#define LPDDR4__DENALI_PI_112_WRITE_MASK 0xFFFFFFFFU

2058

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU

2059

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_SHIFT 0U

2060

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_WIDTH 32U

2061

#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_112

2062

#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0

2063

2064

#define LPDDR4__DENALI_PI_113_READ_MASK 0x00000003U

2065

#define LPDDR4__DENALI_PI_113_WRITE_MASK 0x00000003U

2066

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_MASK 0x00000003U

2067

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_SHIFT 0U

2068

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_WIDTH 2U

2069

#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_113

2070

#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1

2071

2072

#define LPDDR4__DENALI_PI_114_READ_MASK 0xFFFFFFFFU

2073

#define LPDDR4__DENALI_PI_114_WRITE_MASK 0xFFFFFFFFU

2074

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU

2075

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_SHIFT 0U

2076

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_WIDTH 32U

2077

#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_114

2078

#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0

2079

2080

#define LPDDR4__DENALI_PI_115_READ_MASK 0x00000003U

2081

#define LPDDR4__DENALI_PI_115_WRITE_MASK 0x00000003U

2082

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_MASK 0x00000003U

2083

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_SHIFT 0U

2084

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_WIDTH 2U

2085

#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_115

2086

#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1

2087

2088

#define LPDDR4__DENALI_PI_116_READ_MASK 0xFFFFFFFFU

2089

#define LPDDR4__DENALI_PI_116_WRITE_MASK 0xFFFFFFFFU

2090

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU

2091

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_SHIFT 0U

2092

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_WIDTH 32U

2093

#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_116

2094

#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0

2095

2096

#define LPDDR4__DENALI_PI_117_READ_MASK 0x00000003U

2097

#define LPDDR4__DENALI_PI_117_WRITE_MASK 0x00000003U

2098

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_MASK 0x00000003U

2099

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_SHIFT 0U

2100

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_WIDTH 2U

2101

#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_117

2102

#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1

2103

2104

#define LPDDR4__DENALI_PI_118_READ_MASK 0xFFFFFFFFU

2105

#define LPDDR4__DENALI_PI_118_WRITE_MASK 0xFFFFFFFFU

2106

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU

2107

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_SHIFT 0U

2108

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_WIDTH 32U

2109

#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_118

2110

#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0

2111

2112

#define LPDDR4__DENALI_PI_119_READ_MASK 0x00000003U

2113

#define LPDDR4__DENALI_PI_119_WRITE_MASK 0x00000003U

2114

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_MASK 0x00000003U

2115

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_SHIFT 0U

2116

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_WIDTH 2U

2117

#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_119

2118

#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1

2119

2120

#define LPDDR4__DENALI_PI_120_READ_MASK 0xFFFFFFFFU

2121

#define LPDDR4__DENALI_PI_120_WRITE_MASK 0xFFFFFFFFU

2122

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU

2123

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_SHIFT 0U

2124

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_WIDTH 32U

2125

#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_120

2126

#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0

2127

2128

#define LPDDR4__DENALI_PI_121_READ_MASK 0x03030703U

2129

#define LPDDR4__DENALI_PI_121_WRITE_MASK 0x03030703U

2130

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_MASK 0x00000003U

2131

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_SHIFT 0U

2132

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_WIDTH 2U

2133

#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_121

2134

#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1

2135

2136

#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_MASK 0x00000700U

2137

#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_SHIFT 8U

2138

#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_WIDTH 3U

2139

#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_121

2140

#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_MODE

2141

2142

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_MASK 0x00030000U

2143

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_SHIFT 16U

2144

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_WIDTH 2U

2145

#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_121

2146

#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE

2147

2148

#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_MASK 0x03000000U

2149

#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_SHIFT 24U

2150

#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_WIDTH 2U

2151

#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_121

2152

#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE

2153

2154

#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU

2155

#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU

2156

#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU

2157

#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_SHIFT 0U

2158

#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_WIDTH 32U

2159

#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_122

2160

#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0

2161

2162

#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU

2163

#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU

2164

#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU

2165

#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_SHIFT 0U

2166

#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_WIDTH 32U

2167

#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_123

2168

#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1

2169

2170

#define LPDDR4__DENALI_PI_124_READ_MASK 0x0000003FU

2171

#define LPDDR4__DENALI_PI_124_WRITE_MASK 0x0000003FU

2172

#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_MASK 0x0000003FU

2173

#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_SHIFT 0U

2174

#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_WIDTH 6U

2175

#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_124

2176

#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM

2177

2178

#define LPDDR4__DENALI_PI_125_READ_MASK 0x3FFFFFFFU

2179

#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x3FFFFFFFU

2180

#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU

2181

#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_SHIFT 0U

2182

#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_WIDTH 30U

2183

#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_125

2184

#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0

2185

2186

#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU

2187

#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU

2188

#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU

2189

#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_SHIFT 0U

2190

#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_WIDTH 30U

2191

#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_126

2192

#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1

2193

2194

#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU

2195

#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU

2196

#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU

2197

#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_SHIFT 0U

2198

#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_WIDTH 30U

2199

#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_127

2200

#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2

2201

2202

#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU

2203

#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU

2204

#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU

2205

#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_SHIFT 0U

2206

#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_WIDTH 30U

2207

#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_128

2208

#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3

2209

2210

#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU

2211

#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU

2212

#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU

2213

#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_SHIFT 0U

2214

#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_WIDTH 30U

2215

#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_129

2216

#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4

2217

2218

#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU

2219

#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU

2220

#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU

2221

#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_SHIFT 0U

2222

#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_WIDTH 30U

2223

#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_130

2224

#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5

2225

2226

#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU

2227

#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU

2228

#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU

2229

#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_SHIFT 0U

2230

#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_WIDTH 30U

2231

#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_131

2232

#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6

2233

2234

#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU

2235

#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU

2236

#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU

2237

#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_SHIFT 0U

2238

#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_WIDTH 30U

2239

#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_132

2240

#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7

2241

2242

#define LPDDR4__DENALI_PI_133_READ_MASK 0x0101010FU

2243

#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x0101010FU

2244

#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_MASK 0x0000000FU

2245

#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_SHIFT 0U

2246

#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_WIDTH 4U

2247

#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_133

2248

#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_133__PI_COL_DIFF

2249

2250

#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_MASK 0x00000100U

2251

#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_SHIFT 8U

2252

#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WIDTH 1U

2253

#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOCLR 0U

2254

#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOSET 0U

2255

#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_133

2256

#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN

2257

2258

#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_MASK 0x00010000U

2259

#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_SHIFT 16U

2260

#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WIDTH 1U

2261

#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOCLR 0U

2262

#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOSET 0U

2263

#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_133

2264

#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_133__PI_CRC_CALC

2265

2266

#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_MASK 0x01000000U

2267

#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_SHIFT 24U

2268

#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WIDTH 1U

2269

#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOCLR 0U

2270

#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOSET 0U

2271

#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_133

2272

#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN

2273

2274

#define LPDDR4__DENALI_PI_134_READ_MASK 0x00010101U

2275

#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x00010101U

2276

#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_MASK 0x00000001U

2277

#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT 0U

2278

#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH 1U

2279

#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR 0U

2280

#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOSET 0U

2281

#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134

2282

#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT

2283

2284

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00000100U

2285

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 8U

2286

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U

2287

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U

2288

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U

2289

#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134

2290

#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT

2291

2292

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x00010000U

2293

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 16U

2294

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U

2295

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U

2296

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U

2297

#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134

2298

#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH

2299

2300

#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_MASK 0x01000000U

2301

#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_SHIFT 24U

2302

#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WIDTH 1U

2303

#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOCLR 0U

2304

#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOSET 0U

2305

#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_134

2306

#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ

2307

2308

#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010101U

2309

#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010101U

2310

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000001U

2311

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 0U

2312

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U

2313

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U

2314

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U

2315

#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135

2316

#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT

2317

2318

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00000100U

2319

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 8U

2320

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U

2321

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U

2322

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U

2323

#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135

2324

#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT

2325

2326

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x00010000U

2327

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 16U

2328

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U

2329

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U

2330

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U

2331

#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135

2332

#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT

2333

2334

#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_MASK 0x01000000U

2335

#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_SHIFT 24U

2336

#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WIDTH 1U

2337

#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOCLR 0U

2338

#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOSET 0U

2339

#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_135

2340

#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT

2341

2342

#define LPDDR4__DENALI_PI_136_READ_MASK 0xFFFFFFFFU

2343

#define LPDDR4__DENALI_PI_136_WRITE_MASK 0xFFFFFFFFU

2344

#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_MASK 0xFFFFFFFFU

2345

#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_SHIFT 0U

2346

#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_WIDTH 32U

2347

#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_136

2348

#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_136__PI_TRST_PWRON

2349

2350

#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU

2351

#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU

2352

#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU

2353

#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_SHIFT 0U

2354

#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_WIDTH 32U

2355

#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_137

2356

#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE

2357

2358

#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFF0101U

2359

#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFF0101U

2360

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_MASK 0x00000001U

2361

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_SHIFT 0U

2362

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WIDTH 1U

2363

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOCLR 0U

2364

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOSET 0U

2365

#define LPDDR4__PI_DLL_RST__REG DENALI_PI_138

2366

#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST

2367

2368

#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_MASK 0x00000100U

2369

#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_SHIFT 8U

2370

#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WIDTH 1U

2371

#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOCLR 0U

2372

#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOSET 0U

2373

#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_138

2374

#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN

2375

2376

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_MASK 0xFFFF0000U

2377

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_SHIFT 16U

2378

#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_WIDTH 16U

2379

#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_138

2380

#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY

2381

2382

#define LPDDR4__DENALI_PI_139_READ_MASK 0x000000FFU

2383

#define LPDDR4__DENALI_PI_139_WRITE_MASK 0x000000FFU

2384

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU

2385

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_SHIFT 0U

2386

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_WIDTH 8U

2387

#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_139

2388

#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY

2389

2390

#define LPDDR4__DENALI_PI_140_READ_MASK 0x03FFFFFFU

2391

#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x03FFFFFFU

2392

#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_MASK 0x03FFFFFFU

2393

#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_SHIFT 0U

2394

#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_WIDTH 26U

2395

#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_140

2396

#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG

2397

2398

#define LPDDR4__DENALI_PI_141_READ_MASK 0x000001FFU

2399

#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x000001FFU

2400

#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_MASK 0x000000FFU

2401

#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_SHIFT 0U

2402

#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_WIDTH 8U

2403

#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_141

2404

#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_141__PI_MRW_STATUS

2405

2406

#define LPDDR4__DENALI_PI_141__PI_RESERVED27_MASK 0x00000100U

2407

#define LPDDR4__DENALI_PI_141__PI_RESERVED27_SHIFT 8U

2408

#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WIDTH 1U

2409

#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOCLR 0U

2410

#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOSET 0U

2411

#define LPDDR4__PI_RESERVED27__REG DENALI_PI_141

2412

#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_141__PI_RESERVED27

2413

2414

#define LPDDR4__DENALI_PI_142_READ_MASK 0x0001FFFFU

2415

#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x0001FFFFU

2416

#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x0001FFFFU

2417

#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 0U

2418

#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U

2419

#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142

2420

#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG

2421

2422

#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU

2423

#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU

2424

#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU

2425

#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U

2426

#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U

2427

#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143

2428

#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0

2429

2430

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U

2431

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U

2432

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U

2433

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U

2434

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U

2435

#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143

2436

#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT

2437

2438

#define LPDDR4__DENALI_PI_144_READ_MASK 0x01010003U

2439

#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x01010003U

2440

#define LPDDR4__DENALI_PI_144__PI_RESERVED28_MASK 0x00000003U

2441

#define LPDDR4__DENALI_PI_144__PI_RESERVED28_SHIFT 0U

2442

#define LPDDR4__DENALI_PI_144__PI_RESERVED28_WIDTH 2U

2443

#define LPDDR4__PI_RESERVED28__REG DENALI_PI_144

2444

#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_144__PI_RESERVED28

2445

2446

#define LPDDR4__DENALI_PI_144__PI_RESERVED29_MASK 0x00000F00U

2447

#define LPDDR4__DENALI_PI_144__PI_RESERVED29_SHIFT 8U

2448

#define LPDDR4__DENALI_PI_144__PI_RESERVED29_WIDTH 4U

2449

#define LPDDR4__PI_RESERVED29__REG DENALI_PI_144

2450

#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_144__PI_RESERVED29

2451

2452

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U

2453

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U

2454

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U

2455

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U

2456

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U

2457

#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144

2458

#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING

2459

2460

#define LPDDR4__DENALI_PI_144__PI_RESERVED30_MASK 0x01000000U

2461

#define LPDDR4__DENALI_PI_144__PI_RESERVED30_SHIFT 24U

2462

#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WIDTH 1U

2463

#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOCLR 0U

2464

#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOSET 0U

2465

#define LPDDR4__PI_RESERVED30__REG DENALI_PI_144

2466

#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_144__PI_RESERVED30

2467

2468

#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U

2469

#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U

2470

#define LPDDR4__DENALI_PI_145__PI_RESERVED31_MASK 0x00000007U

2471

#define LPDDR4__DENALI_PI_145__PI_RESERVED31_SHIFT 0U

2472

#define LPDDR4__DENALI_PI_145__PI_RESERVED31_WIDTH 3U

2473

#define LPDDR4__PI_RESERVED31__REG DENALI_PI_145

2474

#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_145__PI_RESERVED31

2475

2476

#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U

2477

#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U

2478

#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U

2479

#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145

2480

#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0

2481

2482

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U

2483

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U

2484

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U

2485

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U

2486

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U

2487

#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145

2488

#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0

2489

2490

#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U

2491

#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U

2492

#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U

2493

#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145

2494

#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0

2495

2496

#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU

2497

#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU

2498

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU

2499

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U

2500

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U

2501

#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146

2502

#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1

2503

2504

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U

2505

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U

2506

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U

2507

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U

2508

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U

2509

#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146

2510

#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1

2511

2512

#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U

2513

#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U

2514

#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U

2515

#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146

2516

#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1

2517

2518

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U

2519

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U

2520

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U

2521

#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146

2522

#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2

2523

2524

#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U

2525

#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U

2526

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U

2527

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U

2528

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U

2529

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U

2530

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U

2531

#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147

2532

#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2

2533

2534

#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U

2535

#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U

2536

#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U

2537

#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147

2538

#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2

2539

2540

#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U

2541

#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U

2542

#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U

2543

#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147

2544

#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3

2545

2546

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U

2547

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U

2548

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U

2549

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U

2550

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U

2551

#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147

2552

#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3

2553

2554

#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU

2555

#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU

2556

#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU

2557

#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U

2558

#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U

2559

#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148

2560

#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3

2561

2562

#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U

2563

#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U

2564

#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U

2565

#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148

2566

#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4

2567

2568

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U

2569

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U

2570

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U

2571

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U

2572

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U

2573

#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148

2574

#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4

2575

2576

#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U

2577

#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U

2578

#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U

2579

#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148

2580

#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4

2581

2582

#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU

2583

#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU

2584

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU

2585

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U

2586

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U

2587

#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149

2588

#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5

2589

2590

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U

2591

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U

2592

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U

2593

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U

2594

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U

2595

#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149

2596

#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5

2597

2598

#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U

2599

#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U

2600

#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U

2601

#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149

2602

#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5

2603

2604

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U

2605

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U

2606

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U

2607

#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149

2608

#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6

2609

2610

#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U

2611

#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U

2612

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U

2613

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U

2614

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U

2615

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U

2616

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U

2617

#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150

2618

#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6

2619

2620

#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U

2621

#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U

2622

#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U

2623

#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150

2624

#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6

2625

2626

#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U

2627

#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U

2628

#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U

2629

#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150

2630

#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7

2631

2632

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U

2633

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U

2634

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U

2635

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U

2636

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U

2637

#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150

2638

#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7

2639

2640

#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU

2641

#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU

2642

#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU

2643

#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U

2644

#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U

2645

#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151

2646

#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7

2647

2648

#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU

2649

#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U

2650

#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U

2651

#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152

2652

#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE

2653

2654

#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U

2655

#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U

2656

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U

2657

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U

2658

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U

2659

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U

2660

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U

2661

#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153

2662

#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK

2663

2664

#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U

2665

#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U

2666

#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U

2667

#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153

2668

#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS

2669

2670

#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U

2671

#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U

2672

#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U

2673

#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153

2674

#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM

2675

2676

#define LPDDR4__DENALI_PI_153__PI_RESERVED32_MASK 0x01000000U

2677

#define LPDDR4__DENALI_PI_153__PI_RESERVED32_SHIFT 24U

2678

#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WIDTH 1U

2679

#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOCLR 0U

2680

#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOSET 0U

2681

#define LPDDR4__PI_RESERVED32__REG DENALI_PI_153

2682

#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_153__PI_RESERVED32

2683

2684

#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U

2685

#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U

2686

#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U

2687

#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U

2688

#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U

2689

#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154

2690

#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE

2691

2692

#define LPDDR4__DENALI_PI_154__PI_RESERVED33_MASK 0x00000100U

2693

#define LPDDR4__DENALI_PI_154__PI_RESERVED33_SHIFT 8U

2694

#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WIDTH 1U

2695

#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOCLR 0U

2696

#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOSET 0U

2697

#define LPDDR4__PI_RESERVED33__REG DENALI_PI_154

2698

#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_154__PI_RESERVED33

2699

2700

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U

2701

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U

2702

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U

2703

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U

2704

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U

2705

#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154

2706

#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN

2707

2708

#define LPDDR4__DENALI_PI_154__PI_RESERVED34_MASK 0x01000000U

2709

#define LPDDR4__DENALI_PI_154__PI_RESERVED34_SHIFT 24U

2710

#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WIDTH 1U

2711

#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOCLR 0U

2712

#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOSET 0U

2713

#define LPDDR4__PI_RESERVED34__REG DENALI_PI_154

2714

#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_154__PI_RESERVED34

2715

2716

#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U

2717

#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U

2718

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x00000001U

2719

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 0U

2720

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U

2721

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U

2722

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U

2723

#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155

2724

#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35

2725

2726

#define LPDDR4__DENALI_PI_155__PI_RESERVED36_MASK 0x00000100U

2727

#define LPDDR4__DENALI_PI_155__PI_RESERVED36_SHIFT 8U

2728

#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WIDTH 1U

2729

#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOCLR 0U

2730

#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOSET 0U

2731

#define LPDDR4__PI_RESERVED36__REG DENALI_PI_155

2732

#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_155__PI_RESERVED36

2733

2734

#define LPDDR4__DENALI_PI_155__PI_RESERVED37_MASK 0x00010000U

2735

#define LPDDR4__DENALI_PI_155__PI_RESERVED37_SHIFT 16U

2736

#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WIDTH 1U

2737

#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOCLR 0U

2738

#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOSET 0U

2739

#define LPDDR4__PI_RESERVED37__REG DENALI_PI_155

2740

#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_155__PI_RESERVED37

2741

2742

#define LPDDR4__DENALI_PI_155__PI_RESERVED38_MASK 0x01000000U

2743

#define LPDDR4__DENALI_PI_155__PI_RESERVED38_SHIFT 24U

2744

#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WIDTH 1U

2745

#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOCLR 0U

2746

#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOSET 0U

2747

#define LPDDR4__PI_RESERVED38__REG DENALI_PI_155

2748

#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_155__PI_RESERVED38

2749

2750

#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U

2751

#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U

2752

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x00000001U

2753

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 0U

2754

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U

2755

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U

2756

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U

2757

#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156

2758

#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39

2759

2760

#define LPDDR4__DENALI_PI_156__PI_RESERVED40_MASK 0x00000100U

2761

#define LPDDR4__DENALI_PI_156__PI_RESERVED40_SHIFT 8U

2762

#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WIDTH 1U

2763

#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOCLR 0U

2764

#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOSET 0U

2765

#define LPDDR4__PI_RESERVED40__REG DENALI_PI_156

2766

#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_156__PI_RESERVED40

2767

2768

#define LPDDR4__DENALI_PI_156__PI_RESERVED41_MASK 0x00010000U

2769

#define LPDDR4__DENALI_PI_156__PI_RESERVED41_SHIFT 16U

2770

#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WIDTH 1U

2771

#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOCLR 0U

2772

#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOSET 0U

2773

#define LPDDR4__PI_RESERVED41__REG DENALI_PI_156

2774

#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_156__PI_RESERVED41

2775

2776

#define LPDDR4__DENALI_PI_156__PI_RESERVED42_MASK 0x01000000U

2777

#define LPDDR4__DENALI_PI_156__PI_RESERVED42_SHIFT 24U

2778

#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WIDTH 1U

2779

#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOCLR 0U

2780

#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOSET 0U

2781

#define LPDDR4__PI_RESERVED42__REG DENALI_PI_156

2782

#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_156__PI_RESERVED42

2783

2784

#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U

2785

#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U

2786

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x00000001U

2787

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 0U

2788

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U

2789

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U

2790

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U

2791

#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157

2792

#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43

2793

2794

#define LPDDR4__DENALI_PI_157__PI_RESERVED44_MASK 0x00000100U

2795

#define LPDDR4__DENALI_PI_157__PI_RESERVED44_SHIFT 8U

2796

#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WIDTH 1U

2797

#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOCLR 0U

2798

#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOSET 0U

2799

#define LPDDR4__PI_RESERVED44__REG DENALI_PI_157

2800

#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_157__PI_RESERVED44

2801

2802

#define LPDDR4__DENALI_PI_157__PI_RESERVED45_MASK 0x00010000U

2803

#define LPDDR4__DENALI_PI_157__PI_RESERVED45_SHIFT 16U

2804

#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WIDTH 1U

2805

#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOCLR 0U

2806

#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOSET 0U

2807

#define LPDDR4__PI_RESERVED45__REG DENALI_PI_157

2808

#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_157__PI_RESERVED45

2809

2810

#define LPDDR4__DENALI_PI_157__PI_RESERVED46_MASK 0x01000000U

2811

#define LPDDR4__DENALI_PI_157__PI_RESERVED46_SHIFT 24U

2812

#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WIDTH 1U

2813

#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOCLR 0U

2814

#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOSET 0U

2815

#define LPDDR4__PI_RESERVED46__REG DENALI_PI_157

2816

#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_157__PI_RESERVED46

2817

2818

#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U

2819

#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U

2820

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x00000001U

2821

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 0U

2822

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U

2823

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U

2824

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U

2825

#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158

2826

#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47

2827

2828

#define LPDDR4__DENALI_PI_158__PI_RESERVED48_MASK 0x00000100U

2829

#define LPDDR4__DENALI_PI_158__PI_RESERVED48_SHIFT 8U

2830

#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WIDTH 1U

2831

#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOCLR 0U

2832

#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOSET 0U

2833

#define LPDDR4__PI_RESERVED48__REG DENALI_PI_158

2834

#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_158__PI_RESERVED48

2835

2836

#define LPDDR4__DENALI_PI_158__PI_RESERVED49_MASK 0x00010000U

2837

#define LPDDR4__DENALI_PI_158__PI_RESERVED49_SHIFT 16U

2838

#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WIDTH 1U

2839

#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOCLR 0U

2840

#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOSET 0U

2841

#define LPDDR4__PI_RESERVED49__REG DENALI_PI_158

2842

#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_158__PI_RESERVED49

2843

2844

#define LPDDR4__DENALI_PI_158__PI_RESERVED50_MASK 0x01000000U

2845

#define LPDDR4__DENALI_PI_158__PI_RESERVED50_SHIFT 24U

2846

#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WIDTH 1U

2847

#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOCLR 0U

2848

#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOSET 0U

2849

#define LPDDR4__PI_RESERVED50__REG DENALI_PI_158

2850

#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_158__PI_RESERVED50

2851

2852

#define LPDDR4__DENALI_PI_159_READ_MASK 0x00FF0101U

2853

#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x00FF0101U

2854

#define LPDDR4__DENALI_PI_159__PI_RESERVED51_MASK 0x00000001U

2855

#define LPDDR4__DENALI_PI_159__PI_RESERVED51_SHIFT 0U

2856

#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WIDTH 1U

2857

#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOCLR 0U

2858

#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOSET 0U

2859

#define LPDDR4__PI_RESERVED51__REG DENALI_PI_159

2860

#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_159__PI_RESERVED51

2861

2862

#define LPDDR4__DENALI_PI_159__PI_RESERVED52_MASK 0x00000100U

2863

#define LPDDR4__DENALI_PI_159__PI_RESERVED52_SHIFT 8U

2864

#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WIDTH 1U

2865

#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOCLR 0U

2866

#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOSET 0U

2867

#define LPDDR4__PI_RESERVED52__REG DENALI_PI_159

2868

#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_159__PI_RESERVED52

2869

2870

#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x00FF0000U

2871

#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 16U

2872

#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U

2873

#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159

2874

#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND

2875

2876

#define LPDDR4__DENALI_PI_160_READ_MASK 0x000001FFU

2877

#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x000001FFU

2878

#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_MASK 0x000001FFU

2879

#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_SHIFT 0U

2880

#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_WIDTH 9U

2881

#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_160

2882

#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_160__PI_TREFBW_THR

2883

2884

#define LPDDR4__DENALI_PI_161_READ_MASK 0x0000001FU

2885

#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0000001FU

2886

#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU

2887

#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U

2888

#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U

2889

#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_161

2890

#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY

2891

2892

#define LPDDR4__DENALI_PI_162_READ_MASK 0x01031F01U

2893

#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01031F01U

2894

#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U

2895

#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U

2896

#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U

2897

#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U

2898

#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOSET 0U

2899

#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_162

2900

#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF

2901

2902

#define LPDDR4__DENALI_PI_162__PI_RESERVED53_MASK 0x00001F00U

2903

#define LPDDR4__DENALI_PI_162__PI_RESERVED53_SHIFT 8U

2904

#define LPDDR4__DENALI_PI_162__PI_RESERVED53_WIDTH 5U

2905

#define LPDDR4__PI_RESERVED53__REG DENALI_PI_162

2906

#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_162__PI_RESERVED53

2907

2908

#define LPDDR4__DENALI_PI_162__PI_CATR_MASK 0x00030000U

2909

#define LPDDR4__DENALI_PI_162__PI_CATR_SHIFT 16U

2910

#define LPDDR4__DENALI_PI_162__PI_CATR_WIDTH 2U

2911

#define LPDDR4__PI_CATR__REG DENALI_PI_162

2912

#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_162__PI_CATR

2913

2914

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x01000000U

2915

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 24U

2916

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U

2917

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U

2918

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U

2919

#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162

2920

#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ

2921

2922

#define LPDDR4__DENALI_PI_163_READ_MASK 0x01010101U

2923

#define LPDDR4__DENALI_PI_163_WRITE_MASK 0x01010101U

2924

#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_MASK 0x00000001U

2925

#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_SHIFT 0U

2926

#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WIDTH 1U

2927

#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOCLR 0U

2928

#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOSET 0U

2929

#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_163

2930

#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE

2931

2932

#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_MASK 0x00000100U

2933

#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_SHIFT 8U

2934

#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WIDTH 1U

2935

#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOCLR 0U

2936

#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOSET 0U

2937

#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_163

2938

#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC

2939

2940

#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_MASK 0x00010000U

2941

#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_SHIFT 16U

2942

#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WIDTH 1U

2943

#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOCLR 0U

2944

#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOSET 0U

2945

#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_163

2946

#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ

2947

2948

#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U

2949

#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_SHIFT 24U

2950

#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WIDTH 1U

2951

#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOCLR 0U

2952

#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOSET 0U

2953

#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_163

2954

#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START

2955

2956

#define LPDDR4__DENALI_PI_164_READ_MASK 0x00FFFF07U

2957

#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x00FFFF07U

2958

#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK 0x00000007U

2959

#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT 0U

2960

#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH 3U

2961

#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_164

2962

#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY

2963

2964

#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_MASK 0x00FFFF00U

2965

#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_SHIFT 8U

2966

#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_WIDTH 16U

2967

#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_164

2968

#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_164__PI_TVREF_F0

2969

2970

#define LPDDR4__DENALI_PI_165_READ_MASK 0xFFFFFFFFU

2971

#define LPDDR4__DENALI_PI_165_WRITE_MASK 0xFFFFFFFFU

2972

#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_MASK 0x0000FFFFU

2973

#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_SHIFT 0U

2974

#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_WIDTH 16U

2975

#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_165

2976

#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F1

2977

2978

#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_MASK 0xFFFF0000U

2979

#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_SHIFT 16U

2980

#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_WIDTH 16U

2981

#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_165

2982

#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F2

2983

2984

#define LPDDR4__DENALI_PI_166_READ_MASK 0x00FFFFFFU

2985

#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x00FFFFFFU

2986

#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_MASK 0x000000FFU

2987

#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_SHIFT 0U

2988

#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_WIDTH 8U

2989

#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_166

2990

#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F0

2991

2992

#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_MASK 0x0000FF00U

2993

#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_SHIFT 8U

2994

#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_WIDTH 8U

2995

#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_166

2996

#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F1

2997

2998

#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_MASK 0x00FF0000U

2999

#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_SHIFT 16U

3000

#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_WIDTH 8U

3001

#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_166

3002

#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F2

3003

3004

#define LPDDR4__DENALI_PI_167_READ_MASK 0x000000FFU

3005

#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x000000FFU

3006

#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU

3007

#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U

3008

#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U

3009

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_167

3010

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0

3011

3012

#define LPDDR4__DENALI_PI_168_READ_MASK 0x000000FFU

3013

#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x000000FFU

3014

#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU

3015

#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U

3016

#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U

3017

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_168

3018

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1

3019

3020

#define LPDDR4__DENALI_PI_169_READ_MASK 0x000FFFFFU

3021

#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x000FFFFFU

3022

#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU

3023

#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U

3024

#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U

3025

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_169

3026

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2

3027

3028

#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_MASK 0x000FFF00U

3029

#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_SHIFT 8U

3030

#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_WIDTH 12U

3031

#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_169

3032

#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_169__PI_ZQINIT_F0

3033

3034

#define LPDDR4__DENALI_PI_170_READ_MASK 0x0FFF0FFFU

3035

#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x0FFF0FFFU

3036

#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_MASK 0x00000FFFU

3037

#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_SHIFT 0U

3038

#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_WIDTH 12U

3039

#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_170

3040

#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F1

3041

3042

#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_MASK 0x0FFF0000U

3043

#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_SHIFT 16U

3044

#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_WIDTH 12U

3045

#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_170

3046

#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F2

3047

3048

#define LPDDR4__DENALI_PI_171_READ_MASK 0xFF0F3F7FU

3049

#define LPDDR4__DENALI_PI_171_WRITE_MASK 0xFF0F3F7FU

3050

#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_MASK 0x0000007FU

3051

#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_SHIFT 0U

3052

#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_WIDTH 7U

3053

#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_171

3054

#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_171__PI_WRLAT_F0

3055

3056

#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_MASK 0x00003F00U

3057

#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_SHIFT 8U

3058

#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_WIDTH 6U

3059

#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_171

3060

#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0

3061

3062

#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_MASK 0x000F0000U

3063

#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_SHIFT 16U

3064

#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_WIDTH 4U

3065

#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_171

3066

#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0

3067

3068

#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK 0xFF000000U

3069

#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT 24U

3070

#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH 8U

3071

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_171

3072

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0

3073

3074

#define LPDDR4__DENALI_PI_172_READ_MASK 0x0F3F7F7FU

3075

#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x0F3F7F7FU

3076

#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_MASK 0x0000007FU

3077

#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_SHIFT 0U

3078

#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_WIDTH 7U

3079

#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_172

3080

#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0

3081

3082

#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_MASK 0x00007F00U

3083

#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_SHIFT 8U

3084

#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_WIDTH 7U

3085

#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_172

3086

#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_172__PI_WRLAT_F1

3087

3088

#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_MASK 0x003F0000U

3089

#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_SHIFT 16U

3090

#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_WIDTH 6U

3091

#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_172

3092

#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1

3093

3094

#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_MASK 0x0F000000U

3095

#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_SHIFT 24U

3096

#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_WIDTH 4U

3097

#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_172

3098

#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1

3099

3100

#define LPDDR4__DENALI_PI_173_READ_MASK 0x3F7F7FFFU

3101

#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x3F7F7FFFU

3102

#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK 0x000000FFU

3103

#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT 0U

3104

#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH 8U

3105

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_173

3106

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1

3107

3108

#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_MASK 0x00007F00U

3109

#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_SHIFT 8U

3110

#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_WIDTH 7U

3111

#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_173

3112

#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1

3113

3114

#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_MASK 0x007F0000U

3115

#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_SHIFT 16U

3116

#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_WIDTH 7U

3117

#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_173

3118

#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_173__PI_WRLAT_F2

3119

3120

#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_MASK 0x3F000000U

3121

#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_SHIFT 24U

3122

#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_WIDTH 6U

3123

#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_173

3124

#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2

3125

3126

#define LPDDR4__DENALI_PI_174_READ_MASK 0x007FFF0FU

3127

#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x007FFF0FU

3128

#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_MASK 0x0000000FU

3129

#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_SHIFT 0U

3130

#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_WIDTH 4U

3131

#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_174

3132

#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2

3133

3134

#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK 0x0000FF00U

3135

#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT 8U

3136

#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH 8U

3137

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_174

3138

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2

3139

3140

#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_MASK 0x007F0000U

3141

#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_SHIFT 16U

3142

#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_WIDTH 7U

3143

#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_174

3144

#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2

3145

3146

#define LPDDR4__DENALI_PI_175_READ_MASK 0x000003FFU

3147

#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x000003FFU

3148

#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_MASK 0x000003FFU

3149

#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_SHIFT 0U

3150

#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_WIDTH 10U

3151

#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_175

3152

#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_175__PI_TRFC_F0

3153

3154

#define LPDDR4__DENALI_PI_176_READ_MASK 0x000FFFFFU

3155

#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x000FFFFFU

3156

#define LPDDR4__DENALI_PI_176__PI_TREF_F0_MASK 0x000FFFFFU

3157

#define LPDDR4__DENALI_PI_176__PI_TREF_F0_SHIFT 0U

3158

#define LPDDR4__DENALI_PI_176__PI_TREF_F0_WIDTH 20U

3159

#define LPDDR4__PI_TREF_F0__REG DENALI_PI_176

3160

#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TREF_F0

3161

3162

#define LPDDR4__DENALI_PI_177_READ_MASK 0x000003FFU

3163

#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x000003FFU

3164

#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_MASK 0x000003FFU

3165

#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_SHIFT 0U

3166

#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_WIDTH 10U

3167

#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_177

3168

#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_177__PI_TRFC_F1

3169

3170

#define LPDDR4__DENALI_PI_178_READ_MASK 0x000FFFFFU

3171

#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x000FFFFFU

3172

#define LPDDR4__DENALI_PI_178__PI_TREF_F1_MASK 0x000FFFFFU

3173

#define LPDDR4__DENALI_PI_178__PI_TREF_F1_SHIFT 0U

3174

#define LPDDR4__DENALI_PI_178__PI_TREF_F1_WIDTH 20U

3175

#define LPDDR4__PI_TREF_F1__REG DENALI_PI_178

3176

#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_178__PI_TREF_F1

3177

3178

#define LPDDR4__DENALI_PI_179_READ_MASK 0x000003FFU

3179

#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x000003FFU

3180

#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_MASK 0x000003FFU

3181

#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_SHIFT 0U

3182

#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_WIDTH 10U

3183

#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_179

3184

#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_179__PI_TRFC_F2

3185

3186

#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0FFFFFU

3187

#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0FFFFFU

3188

#define LPDDR4__DENALI_PI_180__PI_TREF_F2_MASK 0x000FFFFFU

3189

#define LPDDR4__DENALI_PI_180__PI_TREF_F2_SHIFT 0U

3190

#define LPDDR4__DENALI_PI_180__PI_TREF_F2_WIDTH 20U

3191

#define LPDDR4__PI_TREF_F2__REG DENALI_PI_180

3192

#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_180__PI_TREF_F2

3193

3194

#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U

3195

#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U

3196

#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U

3197

#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_180

3198

#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0

3199

3200

#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030F0FU

3201

#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030F0FU

3202

#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU

3203

#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U

3204

#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U

3205

#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_181

3206

#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1

3207

3208

#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U

3209

#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U

3210

#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U

3211

#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_181

3212

#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2

3213

3214

#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_MASK 0x00030000U

3215

#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_SHIFT 16U

3216

#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_WIDTH 2U

3217

#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_181

3218

#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0

3219

3220

#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_MASK 0x03000000U

3221

#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_SHIFT 24U

3222

#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_WIDTH 2U

3223

#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_181

3224

#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1

3225

3226

#define LPDDR4__DENALI_PI_182_READ_MASK 0x0003FF03U

3227

#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x0003FF03U

3228

#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_MASK 0x00000003U

3229

#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_SHIFT 0U

3230

#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_WIDTH 2U

3231

#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_182

3232

#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2

3233

3234

#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U

3235

#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_SHIFT 8U

3236

#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_WIDTH 10U

3237

#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_182

3238

#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0

3239

3240

#define LPDDR4__DENALI_PI_183_READ_MASK 0x03FF03FFU

3241

#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03FF03FFU

3242

#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU

3243

#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_SHIFT 0U

3244

#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_WIDTH 10U

3245

#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_183

3246

#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1

3247

3248

#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U

3249

#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_SHIFT 16U

3250

#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_WIDTH 10U

3251

#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_183

3252

#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2

3253

3254

#define LPDDR4__DENALI_PI_184_READ_MASK 0x01FF01FFU

3255

#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x01FF01FFU

3256

#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_MASK 0x000000FFU

3257

#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_SHIFT 0U

3258

#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_WIDTH 8U

3259

#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_184

3260

#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0

3261

3262

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_MASK 0x00000100U

3263

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_SHIFT 8U

3264

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WIDTH 1U

3265

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOCLR 0U

3266

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOSET 0U

3267

#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_184

3268

#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F0

3269

3270

#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_MASK 0x00FF0000U

3271

#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_SHIFT 16U

3272

#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_WIDTH 8U

3273

#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_184

3274

#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1

3275

3276

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_MASK 0x01000000U

3277

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_SHIFT 24U

3278

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WIDTH 1U

3279

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOCLR 0U

3280

#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOSET 0U

3281

#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_184

3282

#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F1

3283

3284

#define LPDDR4__DENALI_PI_185_READ_MASK 0x0F0F01FFU

3285

#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x0F0F01FFU

3286

#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_MASK 0x000000FFU

3287

#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_SHIFT 0U

3288

#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_WIDTH 8U

3289

#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_185

3290

#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2

3291

3292

#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_MASK 0x00000100U

3293

#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_SHIFT 8U

3294

#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WIDTH 1U

3295

#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOCLR 0U

3296

#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOSET 0U

3297

#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_185

3298

#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_ODT_EN_F2

3299

3300

#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_MASK 0x000F0000U

3301

#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_SHIFT 16U

3302

#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_WIDTH 4U

3303

#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_185

3304

#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_185__PI_ODTLON_F0

3305

3306

#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_MASK 0x0F000000U

3307

#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_SHIFT 24U

3308

#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_WIDTH 4U

3309

#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_185

3310

#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0

3311

3312

#define LPDDR4__DENALI_PI_186_READ_MASK 0x0F0F0F0FU

3313

#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x0F0F0F0FU

3314

#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_MASK 0x0000000FU

3315

#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_SHIFT 0U

3316

#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_WIDTH 4U

3317

#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_186

3318

#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F1

3319

3320

#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_MASK 0x00000F00U

3321

#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_SHIFT 8U

3322

#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_WIDTH 4U

3323

#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_186

3324

#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1

3325

3326

#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_MASK 0x000F0000U

3327

#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_SHIFT 16U

3328

#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_WIDTH 4U

3329

#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_186

3330

#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F2

3331

3332

#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_MASK 0x0F000000U

3333

#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_SHIFT 24U

3334

#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_WIDTH 4U

3335

#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_186

3336

#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2

3337

3338

#define LPDDR4__DENALI_PI_187_READ_MASK 0x3F3F3F3FU

3339

#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x3F3F3F3FU

3340

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_MASK 0x0000003FU

3341

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_SHIFT 0U

3342

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_WIDTH 6U

3343

#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_187

3344

#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0

3345

3346

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_MASK 0x00003F00U

3347

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_SHIFT 8U

3348

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_WIDTH 6U

3349

#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_187

3350

#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1

3351

3352

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_MASK 0x003F0000U

3353

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_SHIFT 16U

3354

#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_WIDTH 6U

3355

#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_187

3356

#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2

3357

3358

#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_MASK 0x3F000000U

3359

#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_SHIFT 24U

3360

#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_WIDTH 6U

3361

#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_187

3362

#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0

3363

3364

#define LPDDR4__DENALI_PI_188_READ_MASK 0x03033F3FU

3365

#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03033F3FU

3366

#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_MASK 0x0000003FU

3367

#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_SHIFT 0U

3368

#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_WIDTH 6U

3369

#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_188

3370

#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1

3371

3372

#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_MASK 0x00003F00U

3373

#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_SHIFT 8U

3374

#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_WIDTH 6U

3375

#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_188

3376

#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2

3377

3378

#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_MASK 0x00030000U

3379

#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_SHIFT 16U

3380

#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_WIDTH 2U

3381

#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_188

3382

#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0

3383

3384

#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_MASK 0x03000000U

3385

#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_SHIFT 24U

3386

#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_WIDTH 2U

3387

#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_188

3388

#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0

3389

3390

#define LPDDR4__DENALI_PI_189_READ_MASK 0x03030303U

3391

#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03030303U

3392

#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_MASK 0x00000003U

3393

#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_SHIFT 0U

3394

#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_WIDTH 2U

3395

#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_189

3396

#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1

3397

3398

#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_MASK 0x00000300U

3399

#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_SHIFT 8U

3400

#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_WIDTH 2U

3401

#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_189

3402

#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1

3403

3404

#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_MASK 0x00030000U

3405

#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_SHIFT 16U

3406

#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_WIDTH 2U

3407

#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_189

3408

#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2

3409

3410

#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_MASK 0x03000000U

3411

#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_SHIFT 24U

3412

#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_WIDTH 2U

3413

#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_189

3414

#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2

3415

3416

#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FFFFFFU

3417

#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FFFFFFU

3418

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_MASK 0x000000FFU

3419

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_SHIFT 0U

3420

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_WIDTH 8U

3421

#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_190

3422

#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0

3423

3424

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_MASK 0x0000FF00U

3425

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_SHIFT 8U

3426

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_WIDTH 8U

3427

#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_190

3428

#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1

3429

3430

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_MASK 0x00FF0000U

3431

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_SHIFT 16U

3432

#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_WIDTH 8U

3433

#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_190

3434

#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2

3435

3436

#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_MASK 0x03000000U

3437

#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_SHIFT 24U

3438

#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_WIDTH 2U

3439

#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_190

3440

#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0

3441

3442

#define LPDDR4__DENALI_PI_191_READ_MASK 0x03030303U

3443

#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x03030303U

3444

#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_MASK 0x00000003U

3445

#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_SHIFT 0U

3446

#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U

3447

#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_191

3448

#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0

3449

3450

#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_MASK 0x00000300U

3451

#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_SHIFT 8U

3452

#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_WIDTH 2U

3453

#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_191

3454

#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0

3455

3456

#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_MASK 0x00030000U

3457

#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_SHIFT 16U

3458

#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_WIDTH 2U

3459

#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_191

3460

#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0

3461

3462

#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_MASK 0x03000000U

3463

#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_SHIFT 24U

3464

#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_WIDTH 2U

3465

#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_191

3466

#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1

3467

3468

#define LPDDR4__DENALI_PI_192_READ_MASK 0x03030303U

3469

#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x03030303U

3470

#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_MASK 0x00000003U

3471

#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_SHIFT 0U

3472

#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U

3473

#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_192

3474

#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1

3475

3476

#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_MASK 0x00000300U

3477

#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_SHIFT 8U

3478

#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_WIDTH 2U

3479

#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_192

3480

#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1

3481

3482

#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_MASK 0x00030000U

3483

#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_SHIFT 16U

3484

#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_WIDTH 2U

3485

#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_192

3486

#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1

3487

3488

#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_MASK 0x03000000U

3489

#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_SHIFT 24U

3490

#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_WIDTH 2U

3491

#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_192

3492

#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2

3493

3494

#define LPDDR4__DENALI_PI_193_READ_MASK 0xFF030303U

3495

#define LPDDR4__DENALI_PI_193_WRITE_MASK 0xFF030303U

3496

#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_MASK 0x00000003U

3497

#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_SHIFT 0U

3498

#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U

3499

#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_193

3500

#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2

3501

3502

#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_MASK 0x00000300U

3503

#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_SHIFT 8U

3504

#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_WIDTH 2U

3505

#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_193

3506

#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2

3507

3508

#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_MASK 0x00030000U

3509

#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_SHIFT 16U

3510

#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_WIDTH 2U

3511

#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_193

3512

#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2

3513

3514

#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_MASK 0xFF000000U

3515

#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_SHIFT 24U

3516

#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_WIDTH 8U

3517

#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_193

3518

#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0

3519

3520

#define LPDDR4__DENALI_PI_194_READ_MASK 0xFFFFFFFFU

3521

#define LPDDR4__DENALI_PI_194_WRITE_MASK 0xFFFFFFFFU

3522

#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_MASK 0x000000FFU

3523

#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_SHIFT 0U

3524

#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_WIDTH 8U

3525

#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_194

3526

#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1

3527

3528

#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_MASK 0x0000FF00U

3529

#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_SHIFT 8U

3530

#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_WIDTH 8U

3531

#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_194

3532

#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2

3533

3534

#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_MASK 0x00FF0000U

3535

#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_SHIFT 16U

3536

#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_WIDTH 8U

3537

#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_194

3538

#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0

3539

3540

#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_MASK 0xFF000000U

3541

#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_SHIFT 24U

3542

#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_WIDTH 8U

3543

#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_194

3544

#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1

3545

3546

#define LPDDR4__DENALI_PI_195_READ_MASK 0x070707FFU

3547

#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x070707FFU

3548

#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_MASK 0x000000FFU

3549

#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_SHIFT 0U

3550

#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_WIDTH 8U

3551

#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_195

3552

#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2

3553

3554

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000700U

3555

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_SHIFT 8U

3556

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U

3557

#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_195

3558

#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0

3559

3560

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_MASK 0x00070000U

3561

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_SHIFT 16U

3562

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U

3563

#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_195

3564

#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1

3565

3566

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_MASK 0x07000000U

3567

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_SHIFT 24U

3568

#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U

3569

#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_195

3570

#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2

3571

3572

#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF03FFU

3573

#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF03FFU

3574

#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU

3575

#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_SHIFT 0U

3576

#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_WIDTH 10U

3577

#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_196

3578

#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0

3579

3580

#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U

3581

#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U

3582

#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U

3583

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_196

3584

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0

3585

3586

#define LPDDR4__DENALI_PI_197_READ_MASK 0x03FF03FFU

3587

#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x03FF03FFU

3588

#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU

3589

#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_SHIFT 0U

3590

#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_WIDTH 10U

3591

#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_197

3592

#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1

3593

3594

#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U

3595

#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U

3596

#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U

3597

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_197

3598

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1

3599

3600

#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU

3601

#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU

3602

#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU

3603

#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_SHIFT 0U

3604

#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_WIDTH 10U

3605

#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_198

3606

#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2

3607

3608

#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U

3609

#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U

3610

#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U

3611

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_198

3612

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2

3613

3614

#define LPDDR4__DENALI_PI_199_READ_MASK 0x1F030303U

3615

#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x1F030303U

3616

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_MASK 0x00000003U

3617

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_SHIFT 0U

3618

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_WIDTH 2U

3619

#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_199

3620

#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0

3621

3622

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_MASK 0x00000300U

3623

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_SHIFT 8U

3624

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_WIDTH 2U

3625

#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_199

3626

#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1

3627

3628

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_MASK 0x00030000U

3629

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_SHIFT 16U

3630

#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_WIDTH 2U

3631

#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_199

3632

#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2

3633

3634

#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_MASK 0x1F000000U

3635

#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_SHIFT 24U

3636

#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_WIDTH 5U

3637

#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_199

3638

#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_199__PI_TMRZ_F0

3639

3640

#define LPDDR4__DENALI_PI_200_READ_MASK 0x001F3FFFU

3641

#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x001F3FFFU

3642

#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_MASK 0x00003FFFU

3643

#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_SHIFT 0U

3644

#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_WIDTH 14U

3645

#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_200

3646

#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_200__PI_TCAENT_F0

3647

3648

#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_MASK 0x001F0000U

3649

#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_SHIFT 16U

3650

#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_WIDTH 5U

3651

#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_200

3652

#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_200__PI_TMRZ_F1

3653

3654

#define LPDDR4__DENALI_PI_201_READ_MASK 0x001F3FFFU

3655

#define LPDDR4__DENALI_PI_201_WRITE_MASK 0x001F3FFFU

3656

#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_MASK 0x00003FFFU

3657

#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_SHIFT 0U

3658

#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_WIDTH 14U

3659

#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_201

3660

#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_201__PI_TCAENT_F1

3661

3662

#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_MASK 0x001F0000U

3663

#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_SHIFT 16U

3664

#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_WIDTH 5U

3665

#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_201

3666

#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_201__PI_TMRZ_F2

3667

3668

#define LPDDR4__DENALI_PI_202_READ_MASK 0x1F1F3FFFU

3669

#define LPDDR4__DENALI_PI_202_WRITE_MASK 0x1F1F3FFFU

3670

#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_MASK 0x00003FFFU

3671

#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_SHIFT 0U

3672

#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_WIDTH 14U

3673

#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_202

3674

#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_202__PI_TCAENT_F2

3675

3676

#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_MASK 0x001F0000U

3677

#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_SHIFT 16U

3678

#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_WIDTH 5U

3679

#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_202

3680

#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0

3681

3682

#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_MASK 0x1F000000U

3683

#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_SHIFT 24U

3684

#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_WIDTH 5U

3685

#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_202

3686

#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0

3687

3688

#define LPDDR4__DENALI_PI_203_READ_MASK 0x03FF03FFU

3689

#define LPDDR4__DENALI_PI_203_WRITE_MASK 0x03FF03FFU

3690

#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_MASK 0x000003FFU

3691

#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_SHIFT 0U

3692

#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_WIDTH 10U

3693

#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_203

3694

#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0

3695

3696

#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_MASK 0x03FF0000U

3697

#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_SHIFT 16U

3698

#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_WIDTH 10U

3699

#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_203

3700

#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0

3701

3702

#define LPDDR4__DENALI_PI_204_READ_MASK 0x03FF1F1FU

3703

#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x03FF1F1FU

3704

#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_MASK 0x0000001FU

3705

#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_SHIFT 0U

3706

#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_WIDTH 5U

3707

#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_204

3708

#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1

3709

3710

#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_MASK 0x00001F00U

3711

#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_SHIFT 8U

3712

#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_WIDTH 5U

3713

#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_204

3714

#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1

3715

3716

#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_MASK 0x03FF0000U

3717

#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_SHIFT 16U

3718

#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_WIDTH 10U

3719

#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_204

3720

#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1

3721

3722

#define LPDDR4__DENALI_PI_205_READ_MASK 0x1F1F03FFU

3723

#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x1F1F03FFU

3724

#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_MASK 0x000003FFU

3725

#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_SHIFT 0U

3726

#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_WIDTH 10U

3727

#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_205

3728

#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1

3729

3730

#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_MASK 0x001F0000U

3731

#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_SHIFT 16U

3732

#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_WIDTH 5U

3733

#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_205

3734

#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2

3735

3736

#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_MASK 0x1F000000U

3737

#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_SHIFT 24U

3738

#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_WIDTH 5U

3739

#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_205

3740

#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2

3741

3742

#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FF03FFU

3743

#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FF03FFU

3744

#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_MASK 0x000003FFU

3745

#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_SHIFT 0U

3746

#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_WIDTH 10U

3747

#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_206

3748

#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2

3749

3750

#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_MASK 0x03FF0000U

3751

#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_SHIFT 16U

3752

#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_WIDTH 10U

3753

#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_206

3754

#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2

3755

3756

#define LPDDR4__DENALI_PI_207_READ_MASK 0x7F7F7F7FU

3757

#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x7F7F7F7FU

3758

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU

3759

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U

3760

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U

3761

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_207

3762

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0

3763

3764

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U

3765

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U

3766

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U

3767

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_207

3768

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0

3769

3770

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U

3771

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U

3772

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U

3773

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_207

3774

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1

3775

3776

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U

3777

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U

3778

#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U

3779

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_207

3780

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1

3781

3782

#define LPDDR4__DENALI_PI_208_READ_MASK 0x0F0F7F7FU

3783

#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x0F0F7F7FU

3784

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU

3785

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U

3786

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U

3787

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_208

3788

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2

3789

3790

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U

3791

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U

3792

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U

3793

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_208

3794

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2

3795

3796

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U

3797

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_SHIFT 16U

3798

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_WIDTH 4U

3799

#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_208

3800

#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0

3801

3802

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U

3803

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_SHIFT 24U

3804

#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_WIDTH 4U

3805

#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_208

3806

#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1

3807

3808

#define LPDDR4__DENALI_PI_209_READ_MASK 0xFF1F0F0FU

3809

#define LPDDR4__DENALI_PI_209_WRITE_MASK 0xFF1F0F0FU

3810

#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU

3811

#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_SHIFT 0U

3812

#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_WIDTH 4U

3813

#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_209

3814

#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2

3815

3816

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U

3817

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U

3818

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U

3819

#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_209

3820

#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0

3821

3822

#define LPDDR4__DENALI_PI_209__PI_TXP_F0_MASK 0x001F0000U

3823

#define LPDDR4__DENALI_PI_209__PI_TXP_F0_SHIFT 16U

3824

#define LPDDR4__DENALI_PI_209__PI_TXP_F0_WIDTH 5U

3825

#define LPDDR4__PI_TXP_F0__REG DENALI_PI_209

3826

#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_209__PI_TXP_F0

3827

3828

#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_MASK 0xFF000000U

3829

#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_SHIFT 24U

3830

#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_WIDTH 8U

3831

#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_209

3832

#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0

3833

3834

#define LPDDR4__DENALI_PI_210_READ_MASK 0xFF1F0F1FU

3835

#define LPDDR4__DENALI_PI_210_WRITE_MASK 0xFF1F0F1FU

3836

#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_MASK 0x0000001FU

3837

#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_SHIFT 0U

3838

#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_WIDTH 5U

3839

#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_210

3840

#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_210__PI_TCKELCK_F0

3841

3842

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U

3843

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U

3844

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U

3845

#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_210

3846

#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1

3847

3848

#define LPDDR4__DENALI_PI_210__PI_TXP_F1_MASK 0x001F0000U

3849

#define LPDDR4__DENALI_PI_210__PI_TXP_F1_SHIFT 16U

3850

#define LPDDR4__DENALI_PI_210__PI_TXP_F1_WIDTH 5U

3851

#define LPDDR4__PI_TXP_F1__REG DENALI_PI_210

3852

#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_210__PI_TXP_F1

3853

3854

#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_MASK 0xFF000000U

3855

#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_SHIFT 24U

3856

#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_WIDTH 8U

3857

#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_210

3858

#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1

3859

3860

#define LPDDR4__DENALI_PI_211_READ_MASK 0xFF1F0F1FU

3861

#define LPDDR4__DENALI_PI_211_WRITE_MASK 0xFF1F0F1FU

3862

#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_MASK 0x0000001FU

3863

#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_SHIFT 0U

3864

#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_WIDTH 5U

3865

#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_211

3866

#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_211__PI_TCKELCK_F1

3867

3868

#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U

3869

#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U

3870

#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U

3871

#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_211

3872

#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2

3873

3874

#define LPDDR4__DENALI_PI_211__PI_TXP_F2_MASK 0x001F0000U

3875

#define LPDDR4__DENALI_PI_211__PI_TXP_F2_SHIFT 16U

3876

#define LPDDR4__DENALI_PI_211__PI_TXP_F2_WIDTH 5U

3877

#define LPDDR4__PI_TXP_F2__REG DENALI_PI_211

3878

#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_211__PI_TXP_F2

3879

3880

#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_MASK 0xFF000000U

3881

#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_SHIFT 24U

3882

#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_WIDTH 8U

3883

#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_211

3884

#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2

3885

3886

#define LPDDR4__DENALI_PI_212_READ_MASK 0xFFFFFF1FU

3887

#define LPDDR4__DENALI_PI_212_WRITE_MASK 0xFFFFFF1FU

3888

#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_MASK 0x0000001FU

3889

#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_SHIFT 0U

3890

#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_WIDTH 5U

3891

#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_212

3892

#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_212__PI_TCKELCK_F2

3893

3894

#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_MASK 0xFFFFFF00U

3895

#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_SHIFT 8U

3896

#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_WIDTH 24U

3897

#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_212

3898

#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0

3899

3900

#define LPDDR4__DENALI_PI_213_READ_MASK 0x00FFFFFFU

3901

#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x00FFFFFFU

3902

#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU

3903

#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U

3904

#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_WIDTH 24U

3905

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_213

3906

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0

3907

3908

#define LPDDR4__DENALI_PI_214_READ_MASK 0x00FFFFFFU

3909

#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x00FFFFFFU

3910

#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_MASK 0x00FFFFFFU

3911

#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_SHIFT 0U

3912

#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_WIDTH 24U

3913

#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_214

3914

#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1

3915

3916

#define LPDDR4__DENALI_PI_215_READ_MASK 0x00FFFFFFU

3917

#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x00FFFFFFU

3918

#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU

3919

#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U

3920

#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_WIDTH 24U

3921

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_215

3922

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1

3923

3924

#define LPDDR4__DENALI_PI_216_READ_MASK 0x00FFFFFFU

3925

#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x00FFFFFFU

3926

#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_MASK 0x00FFFFFFU

3927

#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_SHIFT 0U

3928

#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_WIDTH 24U

3929

#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_216

3930

#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2

3931

3932

#define LPDDR4__DENALI_PI_217_READ_MASK 0x3FFFFFFFU

3933

#define LPDDR4__DENALI_PI_217_WRITE_MASK 0x3FFFFFFFU

3934

#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU

3935

#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U

3936

#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_WIDTH 24U

3937

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_217

3938

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2

3939

3940

#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_MASK 0x3F000000U

3941

#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_SHIFT 24U

3942

#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_WIDTH 6U

3943

#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_217

3944

#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0

3945

3946

#define LPDDR4__DENALI_PI_218_READ_MASK 0x003F03FFU

3947

#define LPDDR4__DENALI_PI_218_WRITE_MASK 0x003F03FFU

3948

#define LPDDR4__DENALI_PI_218__PI_TFC_F0_MASK 0x000003FFU

3949

#define LPDDR4__DENALI_PI_218__PI_TFC_F0_SHIFT 0U

3950

#define LPDDR4__DENALI_PI_218__PI_TFC_F0_WIDTH 10U

3951

#define LPDDR4__PI_TFC_F0__REG DENALI_PI_218

3952

#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_218__PI_TFC_F0

3953

3954

#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_MASK 0x003F0000U

3955

#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_SHIFT 16U

3956

#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_WIDTH 6U

3957

#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_218

3958

#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1

3959

3960

#define LPDDR4__DENALI_PI_219_READ_MASK 0x003F03FFU

3961

#define LPDDR4__DENALI_PI_219_WRITE_MASK 0x003F03FFU

3962

#define LPDDR4__DENALI_PI_219__PI_TFC_F1_MASK 0x000003FFU

3963

#define LPDDR4__DENALI_PI_219__PI_TFC_F1_SHIFT 0U

3964

#define LPDDR4__DENALI_PI_219__PI_TFC_F1_WIDTH 10U

3965

#define LPDDR4__PI_TFC_F1__REG DENALI_PI_219

3966

#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_219__PI_TFC_F1

3967

3968

#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_MASK 0x003F0000U

3969

#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_SHIFT 16U

3970

#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_WIDTH 6U

3971

#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_219

3972

#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2

3973

3974

#define LPDDR4__DENALI_PI_220_READ_MASK 0x030303FFU

3975

#define LPDDR4__DENALI_PI_220_WRITE_MASK 0x030303FFU

3976

#define LPDDR4__DENALI_PI_220__PI_TFC_F2_MASK 0x000003FFU

3977

#define LPDDR4__DENALI_PI_220__PI_TFC_F2_SHIFT 0U

3978

#define LPDDR4__DENALI_PI_220__PI_TFC_F2_WIDTH 10U

3979

#define LPDDR4__PI_TFC_F2__REG DENALI_PI_220

3980

#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_220__PI_TFC_F2

3981

3982

#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_MASK 0x00030000U

3983

#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_SHIFT 16U

3984

#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_WIDTH 2U

3985

#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_220

3986

#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F0

3987

3988

#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_MASK 0x03000000U

3989

#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_SHIFT 24U

3990

#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_WIDTH 2U

3991

#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_220

3992

#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F1

3993

3994

#define LPDDR4__DENALI_PI_221_READ_MASK 0x0003FF03U

3995

#define LPDDR4__DENALI_PI_221_WRITE_MASK 0x0003FF03U

3996

#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_MASK 0x00000003U

3997

#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_SHIFT 0U

3998

#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_WIDTH 2U

3999

#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_221

4000

#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_221__PI_VREF_EN_F2

4001

4002

#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_MASK 0x0003FF00U

4003

#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_SHIFT 8U

4004

#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U

4005

#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_221

4006

#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0

4007

4008

#define LPDDR4__DENALI_PI_222_READ_MASK 0x7F7F03FFU

4009

#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x7F7F03FFU

4010

#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU

4011

#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U

4012

#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U

4013

#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_222

4014

#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0

4015

4016

#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U

4017

#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U

4018

#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U

4019

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_222

4020

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0

4021

4022

#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U

4023

#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U

4024

#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U

4025

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_222

4026

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0

4027

4028

#define LPDDR4__DENALI_PI_223_READ_MASK 0x1F03030FU

4029

#define LPDDR4__DENALI_PI_223_WRITE_MASK 0x1F03030FU

4030

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU

4031

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U

4032

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U

4033

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_223

4034

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0

4035

4036

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_MASK 0x00000300U

4037

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_SHIFT 8U

4038

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_WIDTH 2U

4039

#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_223

4040

#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0

4041

4042

#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U

4043

#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_SHIFT 16U

4044

#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_WIDTH 2U

4045

#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_223

4046

#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0

4047

4048

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_MASK 0x1F000000U

4049

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_SHIFT 24U

4050

#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_WIDTH 5U

4051

#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_223

4052

#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0

4053

4054

#define LPDDR4__DENALI_PI_224_READ_MASK 0x03FFFFFFU

4055

#define LPDDR4__DENALI_PI_224_WRITE_MASK 0x03FFFFFFU

4056

#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_MASK 0x000000FFU

4057

#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT 0U

4058

#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH 8U

4059

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_224

4060

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0

4061

4062

#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_MASK 0x0000FF00U

4063

#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT 8U

4064

#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH 8U

4065

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_224

4066

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0

4067

4068

#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_MASK 0x03FF0000U

4069

#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_SHIFT 16U

4070

#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U

4071

#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_224

4072

#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1

4073

4074

#define LPDDR4__DENALI_PI_225_READ_MASK 0x7F7F03FFU

4075

#define LPDDR4__DENALI_PI_225_WRITE_MASK 0x7F7F03FFU

4076

#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_MASK 0x000003FFU

4077

#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_SHIFT 0U

4078

#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U

4079

#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_225

4080

#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1

4081

4082

#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U

4083

#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U

4084

#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U

4085

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_225

4086

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1

4087

4088

#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U

4089

#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U

4090

#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U

4091

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_225

4092

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1

4093

4094

#define LPDDR4__DENALI_PI_226_READ_MASK 0x1F03030FU

4095

#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x1F03030FU

4096

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_MASK 0x0000000FU

4097

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_SHIFT 0U

4098

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U

4099

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_226

4100

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1

4101

4102

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_MASK 0x00000300U

4103

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_SHIFT 8U

4104

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_WIDTH 2U

4105

#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_226

4106

#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1

4107

4108

#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_MASK 0x00030000U

4109

#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_SHIFT 16U

4110

#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_WIDTH 2U

4111

#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_226

4112

#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1

4113

4114

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_MASK 0x1F000000U

4115

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_SHIFT 24U

4116

#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_WIDTH 5U

4117

#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_226

4118

#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1

4119

4120

#define LPDDR4__DENALI_PI_227_READ_MASK 0x03FFFFFFU

4121

#define LPDDR4__DENALI_PI_227_WRITE_MASK 0x03FFFFFFU

4122

#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_MASK 0x000000FFU

4123

#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT 0U

4124

#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH 8U

4125

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_227

4126

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1

4127

4128

#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_MASK 0x0000FF00U

4129

#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT 8U

4130

#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH 8U

4131

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_227

4132

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1

4133

4134

#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_MASK 0x03FF0000U

4135

#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_SHIFT 16U

4136

#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U

4137

#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_227

4138

#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2

4139

4140

#define LPDDR4__DENALI_PI_228_READ_MASK 0x7F7F03FFU

4141

#define LPDDR4__DENALI_PI_228_WRITE_MASK 0x7F7F03FFU

4142

#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU

4143

#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U

4144

#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U

4145

#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_228

4146

#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2

4147

4148

#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U

4149

#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U

4150

#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U

4151

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_228

4152

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2

4153

4154

#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U

4155

#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U

4156

#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U

4157

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_228

4158

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2

4159

4160

#define LPDDR4__DENALI_PI_229_READ_MASK 0x1F03030FU

4161

#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1F03030FU

4162

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU

4163

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U

4164

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U

4165

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_229

4166

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2

4167

4168

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_MASK 0x00000300U

4169

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_SHIFT 8U

4170

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_WIDTH 2U

4171

#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_229

4172

#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2

4173

4174

#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U

4175

#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_SHIFT 16U

4176

#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_WIDTH 2U

4177

#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_229

4178

#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2

4179

4180

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_MASK 0x1F000000U

4181

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_SHIFT 24U

4182

#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_WIDTH 5U

4183

#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_229

4184

#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2

4185

4186

#define LPDDR4__DENALI_PI_230_READ_MASK 0x0303FFFFU

4187

#define LPDDR4__DENALI_PI_230_WRITE_MASK 0x0303FFFFU

4188

#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_MASK 0x000000FFU

4189

#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT 0U

4190

#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH 8U

4191

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_230

4192

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2

4193

4194

#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_MASK 0x0000FF00U

4195

#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT 8U

4196

#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH 8U

4197

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_230

4198

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2

4199

4200

#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_MASK 0x00030000U

4201

#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_SHIFT 16U

4202

#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_WIDTH 2U

4203

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_230

4204

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0

4205

4206

#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_MASK 0x03000000U

4207

#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_SHIFT 24U

4208

#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_WIDTH 2U

4209

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_230

4210

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1

4211

4212

#define LPDDR4__DENALI_PI_231_READ_MASK 0xFFFFFF03U

4213

#define LPDDR4__DENALI_PI_231_WRITE_MASK 0xFFFFFF03U

4214

#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_MASK 0x00000003U

4215

#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_SHIFT 0U

4216

#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_WIDTH 2U

4217

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_231

4218

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2

4219

4220

#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_MASK 0x0000FF00U

4221

#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_SHIFT 8U

4222

#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_WIDTH 8U

4223

#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_231

4224

#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRTP_F0

4225

4226

#define LPDDR4__DENALI_PI_231__PI_TRP_F0_MASK 0x00FF0000U

4227

#define LPDDR4__DENALI_PI_231__PI_TRP_F0_SHIFT 16U

4228

#define LPDDR4__DENALI_PI_231__PI_TRP_F0_WIDTH 8U

4229

#define LPDDR4__PI_TRP_F0__REG DENALI_PI_231

4230

#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRP_F0

4231

4232

#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_MASK 0xFF000000U

4233

#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_SHIFT 24U

4234

#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_WIDTH 8U

4235

#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_231

4236

#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_231__PI_TRCD_F0

4237

4238

#define LPDDR4__DENALI_PI_232_READ_MASK 0x00FF3F1FU

4239

#define LPDDR4__DENALI_PI_232_WRITE_MASK 0x00FF3F1FU

4240

#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_MASK 0x0000001FU

4241

#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_SHIFT 0U

4242

#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_WIDTH 5U

4243

#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_232

4244

#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_232__PI_TCCD_L_F0

4245

4246

#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_MASK 0x00003F00U

4247

#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_SHIFT 8U

4248

#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_WIDTH 6U

4249

#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_232

4250

#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWTR_F0

4251

4252

#define LPDDR4__DENALI_PI_232__PI_TWR_F0_MASK 0x00FF0000U

4253

#define LPDDR4__DENALI_PI_232__PI_TWR_F0_SHIFT 16U

4254

#define LPDDR4__DENALI_PI_232__PI_TWR_F0_WIDTH 8U

4255

#define LPDDR4__PI_TWR_F0__REG DENALI_PI_232

4256

#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWR_F0

4257

4258

#define LPDDR4__DENALI_PI_233_READ_MASK 0x000FFFFFU

4259

#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x000FFFFFU

4260

#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_MASK 0x000FFFFFU

4261

#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_SHIFT 0U

4262

#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_WIDTH 20U

4263

#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_233

4264

#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0

4265

4266

#define LPDDR4__DENALI_PI_234_READ_MASK 0x3F0F01FFU

4267

#define LPDDR4__DENALI_PI_234_WRITE_MASK 0x3F0F01FFU

4268

#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_MASK 0x000001FFU

4269

#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_SHIFT 0U

4270

#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_WIDTH 9U

4271

#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_234

4272

#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0

4273

4274

#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_MASK 0x000F0000U

4275

#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_SHIFT 16U

4276

#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_WIDTH 4U

4277

#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_234

4278

#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0

4279

4280

#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_MASK 0x3F000000U

4281

#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_SHIFT 24U

4282

#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_WIDTH 6U

4283

#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_234

4284

#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_234__PI_TCCDMW_F0

4285

4286

#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU

4287

#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU

4288

#define LPDDR4__DENALI_PI_235__PI_TSR_F0_MASK 0x000000FFU

4289

#define LPDDR4__DENALI_PI_235__PI_TSR_F0_SHIFT 0U

4290

#define LPDDR4__DENALI_PI_235__PI_TSR_F0_WIDTH 8U

4291

#define LPDDR4__PI_TSR_F0__REG DENALI_PI_235

4292

#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TSR_F0

4293

4294

#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_MASK 0x0000FF00U

4295

#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_SHIFT 8U

4296

#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_WIDTH 8U

4297

#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_235

4298

#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRD_F0

4299

4300

#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_MASK 0x00FF0000U

4301

#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_SHIFT 16U

4302

#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_WIDTH 8U

4303

#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_235

4304

#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRW_F0

4305

4306

#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_MASK 0xFF000000U

4307

#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_SHIFT 24U

4308

#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_WIDTH 8U

4309

#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_235

4310

#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMOD_F0

4311

4312

#define LPDDR4__DENALI_PI_236_READ_MASK 0xFFFFFFFFU

4313

#define LPDDR4__DENALI_PI_236_WRITE_MASK 0xFFFFFFFFU

4314

#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_MASK 0x000000FFU

4315

#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_SHIFT 0U

4316

#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_WIDTH 8U

4317

#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_236

4318

#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0

4319

4320

#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_MASK 0x0000FF00U

4321

#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_SHIFT 8U

4322

#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_WIDTH 8U

4323

#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_236

4324

#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0

4325

4326

#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_MASK 0x00FF0000U

4327

#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_SHIFT 16U

4328

#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_WIDTH 8U

4329

#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_236

4330

#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRTP_F1

4331

4332

#define LPDDR4__DENALI_PI_236__PI_TRP_F1_MASK 0xFF000000U

4333

#define LPDDR4__DENALI_PI_236__PI_TRP_F1_SHIFT 24U

4334

#define LPDDR4__DENALI_PI_236__PI_TRP_F1_WIDTH 8U

4335

#define LPDDR4__PI_TRP_F1__REG DENALI_PI_236

4336

#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRP_F1

4337

4338

#define LPDDR4__DENALI_PI_237_READ_MASK 0xFF3F1FFFU

4339

#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFF3F1FFFU

4340

#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_MASK 0x000000FFU

4341

#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_SHIFT 0U

4342

#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_WIDTH 8U

4343

#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_237

4344

#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_237__PI_TRCD_F1

4345

4346

#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_MASK 0x00001F00U

4347

#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_SHIFT 8U

4348

#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_WIDTH 5U

4349

#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_237

4350

#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_237__PI_TCCD_L_F1

4351

4352

#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_MASK 0x003F0000U

4353

#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_SHIFT 16U

4354

#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_WIDTH 6U

4355

#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_237

4356

#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWTR_F1

4357

4358

#define LPDDR4__DENALI_PI_237__PI_TWR_F1_MASK 0xFF000000U

4359

#define LPDDR4__DENALI_PI_237__PI_TWR_F1_SHIFT 24U

4360

#define LPDDR4__DENALI_PI_237__PI_TWR_F1_WIDTH 8U

4361

#define LPDDR4__PI_TWR_F1__REG DENALI_PI_237

4362

#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWR_F1

4363

4364

#define LPDDR4__DENALI_PI_238_READ_MASK 0x000FFFFFU

4365

#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x000FFFFFU

4366

#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_MASK 0x000FFFFFU

4367

#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_SHIFT 0U

4368

#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_WIDTH 20U

4369

#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_238

4370

#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1

4371

4372

#define LPDDR4__DENALI_PI_239_READ_MASK 0x3F0F01FFU

4373

#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x3F0F01FFU

4374

#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_MASK 0x000001FFU

4375

#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_SHIFT 0U

4376

#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_WIDTH 9U

4377

#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_239

4378

#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1

4379

4380

#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_MASK 0x000F0000U

4381

#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_SHIFT 16U

4382

#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_WIDTH 4U

4383

#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_239

4384

#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1

4385

4386

#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_MASK 0x3F000000U

4387

#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_SHIFT 24U

4388

#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_WIDTH 6U

4389

#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_239

4390

#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_239__PI_TCCDMW_F1

4391

4392

#define LPDDR4__DENALI_PI_240_READ_MASK 0xFFFFFFFFU

4393

#define LPDDR4__DENALI_PI_240_WRITE_MASK 0xFFFFFFFFU

4394

#define LPDDR4__DENALI_PI_240__PI_TSR_F1_MASK 0x000000FFU

4395

#define LPDDR4__DENALI_PI_240__PI_TSR_F1_SHIFT 0U

4396

#define LPDDR4__DENALI_PI_240__PI_TSR_F1_WIDTH 8U

4397

#define LPDDR4__PI_TSR_F1__REG DENALI_PI_240

4398

#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_240__PI_TSR_F1

4399

4400

#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_MASK 0x0000FF00U

4401

#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_SHIFT 8U

4402

#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_WIDTH 8U

4403

#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_240

4404

#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRD_F1

4405

4406

#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_MASK 0x00FF0000U

4407

#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_SHIFT 16U

4408

#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_WIDTH 8U

4409

#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_240

4410

#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRW_F1

4411

4412

#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_MASK 0xFF000000U

4413

#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_SHIFT 24U

4414

#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_WIDTH 8U

4415

#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_240

4416

#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMOD_F1

4417

4418

#define LPDDR4__DENALI_PI_241_READ_MASK 0xFFFFFFFFU

4419

#define LPDDR4__DENALI_PI_241_WRITE_MASK 0xFFFFFFFFU

4420

#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_MASK 0x000000FFU

4421

#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_SHIFT 0U

4422

#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_WIDTH 8U

4423

#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_241

4424

#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1

4425

4426

#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_MASK 0x0000FF00U

4427

#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_SHIFT 8U

4428

#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_WIDTH 8U

4429

#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_241

4430

#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1

4431

4432

#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_MASK 0x00FF0000U

4433

#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_SHIFT 16U

4434

#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_WIDTH 8U

4435

#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_241

4436

#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRTP_F2

4437

4438

#define LPDDR4__DENALI_PI_241__PI_TRP_F2_MASK 0xFF000000U

4439

#define LPDDR4__DENALI_PI_241__PI_TRP_F2_SHIFT 24U

4440

#define LPDDR4__DENALI_PI_241__PI_TRP_F2_WIDTH 8U

4441

#define LPDDR4__PI_TRP_F2__REG DENALI_PI_241

4442

#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRP_F2

4443

4444

#define LPDDR4__DENALI_PI_242_READ_MASK 0xFF3F1FFFU

4445

#define LPDDR4__DENALI_PI_242_WRITE_MASK 0xFF3F1FFFU

4446

#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_MASK 0x000000FFU

4447

#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_SHIFT 0U

4448

#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_WIDTH 8U

4449

#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_242

4450

#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_242__PI_TRCD_F2

4451

4452

#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_MASK 0x00001F00U

4453

#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_SHIFT 8U

4454

#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_WIDTH 5U

4455

#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_242

4456

#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_242__PI_TCCD_L_F2

4457

4458

#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_MASK 0x003F0000U

4459

#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_SHIFT 16U

4460

#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_WIDTH 6U

4461

#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_242

4462

#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWTR_F2

4463

4464

#define LPDDR4__DENALI_PI_242__PI_TWR_F2_MASK 0xFF000000U

4465

#define LPDDR4__DENALI_PI_242__PI_TWR_F2_SHIFT 24U

4466

#define LPDDR4__DENALI_PI_242__PI_TWR_F2_WIDTH 8U

4467

#define LPDDR4__PI_TWR_F2__REG DENALI_PI_242

4468

#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWR_F2

4469

4470

#define LPDDR4__DENALI_PI_243_READ_MASK 0x000FFFFFU

4471

#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x000FFFFFU

4472

#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_MASK 0x000FFFFFU

4473

#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_SHIFT 0U

4474

#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_WIDTH 20U

4475

#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_243

4476

#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2

4477

4478

#define LPDDR4__DENALI_PI_244_READ_MASK 0x3F0F01FFU

4479

#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x3F0F01FFU

4480

#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_MASK 0x000001FFU

4481

#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_SHIFT 0U

4482

#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_WIDTH 9U

4483

#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_244

4484

#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2

4485

4486

#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_MASK 0x000F0000U

4487

#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_SHIFT 16U

4488

#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_WIDTH 4U

4489

#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_244

4490

#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2

4491

4492

#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_MASK 0x3F000000U

4493

#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_SHIFT 24U

4494

#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_WIDTH 6U

4495

#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_244

4496

#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_244__PI_TCCDMW_F2

4497

4498

#define LPDDR4__DENALI_PI_245_READ_MASK 0xFFFFFFFFU

4499

#define LPDDR4__DENALI_PI_245_WRITE_MASK 0xFFFFFFFFU

4500

#define LPDDR4__DENALI_PI_245__PI_TSR_F2_MASK 0x000000FFU

4501

#define LPDDR4__DENALI_PI_245__PI_TSR_F2_SHIFT 0U

4502

#define LPDDR4__DENALI_PI_245__PI_TSR_F2_WIDTH 8U

4503

#define LPDDR4__PI_TSR_F2__REG DENALI_PI_245

4504

#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_245__PI_TSR_F2

4505

4506

#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_MASK 0x0000FF00U

4507

#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_SHIFT 8U

4508

#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_WIDTH 8U

4509

#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_245

4510

#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRD_F2

4511

4512

#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_MASK 0x00FF0000U

4513

#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_SHIFT 16U

4514

#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_WIDTH 8U

4515

#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_245

4516

#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRW_F2

4517

4518

#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_MASK 0xFF000000U

4519

#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_SHIFT 24U

4520

#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_WIDTH 8U

4521

#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_245

4522

#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMOD_F2

4523

4524

#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU

4525

#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU

4526

#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_MASK 0x000000FFU

4527

#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_SHIFT 0U

4528

#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_WIDTH 8U

4529

#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_246

4530

#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2

4531

4532

#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_MASK 0x0000FF00U

4533

#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_SHIFT 8U

4534

#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_WIDTH 8U

4535

#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_246

4536

#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2

4537

4538

#define LPDDR4__DENALI_PI_247_READ_MASK 0x001FFFFFU

4539

#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x001FFFFFU

4540

#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU

4541

#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 0U

4542

#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U

4543

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_247

4544

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0

4545

4546

#define LPDDR4__DENALI_PI_248_READ_MASK 0xFFFFFFFFU

4547

#define LPDDR4__DENALI_PI_248_WRITE_MASK 0xFFFFFFFFU

4548

#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU

4549

#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U

4550

#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U

4551

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_248

4552

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0

4553

4554

#define LPDDR4__DENALI_PI_249_READ_MASK 0x001FFFFFU

4555

#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x001FFFFFU

4556

#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU

4557

#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U

4558

#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U

4559

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_249

4560

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1

4561

4562

#define LPDDR4__DENALI_PI_250_READ_MASK 0xFFFFFFFFU

4563

#define LPDDR4__DENALI_PI_250_WRITE_MASK 0xFFFFFFFFU

4564

#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU

4565

#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U

4566

#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U

4567

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_250

4568

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1

4569

4570

#define LPDDR4__DENALI_PI_251_READ_MASK 0x001FFFFFU

4571

#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x001FFFFFU

4572

#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU

4573

#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U

4574

#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U

4575

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_251

4576

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2

4577

4578

#define LPDDR4__DENALI_PI_252_READ_MASK 0xFFFFFFFFU

4579

#define LPDDR4__DENALI_PI_252_WRITE_MASK 0xFFFFFFFFU

4580

#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU

4581

#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U

4582

#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U

4583

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_252

4584

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2

4585

4586

#define LPDDR4__DENALI_PI_253_READ_MASK 0xFFFFFFFFU

4587

#define LPDDR4__DENALI_PI_253_WRITE_MASK 0xFFFFFFFFU

4588

#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_MASK 0x0000FFFFU

4589

#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_SHIFT 0U

4590

#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_WIDTH 16U

4591

#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_253

4592

#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F0

4593

4594

#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_MASK 0xFFFF0000U

4595

#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_SHIFT 16U

4596

#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_WIDTH 16U

4597

#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_253

4598

#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F1

4599

4600

#define LPDDR4__DENALI_PI_254_READ_MASK 0x3F3FFFFFU

4601

#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x3F3FFFFFU

4602

#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_MASK 0x0000FFFFU

4603

#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_SHIFT 0U

4604

#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_WIDTH 16U

4605

#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_254

4606

#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_254__PI_TXSR_F2

4607

4608

#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_MASK 0x003F0000U

4609

#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_SHIFT 16U

4610

#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_WIDTH 6U

4611

#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_254

4612

#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F0

4613

4614

#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_MASK 0x3F000000U

4615

#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_SHIFT 24U

4616

#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_WIDTH 6U

4617

#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_254

4618

#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F1

4619

4620

#define LPDDR4__DENALI_PI_255_READ_MASK 0x00FFFF3FU

4621

#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x00FFFF3FU

4622

#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_MASK 0x0000003FU

4623

#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_SHIFT 0U

4624

#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_WIDTH 6U

4625

#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_255

4626

#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_255__PI_TEXCKE_F2

4627

4628

#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_MASK 0x00FFFF00U

4629

#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_SHIFT 8U

4630

#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_WIDTH 16U

4631

#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_255

4632

#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_255__PI_TDLL_F0

4633

4634

#define LPDDR4__DENALI_PI_256_READ_MASK 0xFFFFFFFFU

4635

#define LPDDR4__DENALI_PI_256_WRITE_MASK 0xFFFFFFFFU

4636

#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_MASK 0x0000FFFFU

4637

#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_SHIFT 0U

4638

#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_WIDTH 16U

4639

#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_256

4640

#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F1

4641

4642

#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_MASK 0xFFFF0000U

4643

#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_SHIFT 16U

4644

#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_WIDTH 16U

4645

#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_256

4646

#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F2

4647

4648

#define LPDDR4__DENALI_PI_257_READ_MASK 0xFFFFFFFFU

4649

#define LPDDR4__DENALI_PI_257_WRITE_MASK 0xFFFFFFFFU

4650

#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_MASK 0x000000FFU

4651

#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_SHIFT 0U

4652

#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_WIDTH 8U

4653

#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_257

4654

#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F0

4655

4656

#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_MASK 0x0000FF00U

4657

#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_SHIFT 8U

4658

#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_WIDTH 8U

4659

#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_257

4660

#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F0

4661

4662

#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_MASK 0x00FF0000U

4663

#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_SHIFT 16U

4664

#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_WIDTH 8U

4665

#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_257

4666

#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F1

4667

4668

#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_MASK 0xFF000000U

4669

#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_SHIFT 24U

4670

#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_WIDTH 8U

4671

#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_257

4672

#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F1

4673

4674

#define LPDDR4__DENALI_PI_258_READ_MASK 0x0000FFFFU

4675

#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0000FFFFU

4676

#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_MASK 0x000000FFU

4677

#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_SHIFT 0U

4678

#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_WIDTH 8U

4679

#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_258

4680

#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRX_F2

4681

4682

#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_MASK 0x0000FF00U

4683

#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_SHIFT 8U

4684

#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_WIDTH 8U

4685

#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_258

4686

#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRE_F2

4687

4688

#define LPDDR4__DENALI_PI_259_READ_MASK 0x00FFFFFFU

4689

#define LPDDR4__DENALI_PI_259_WRITE_MASK 0x00FFFFFFU

4690

#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_MASK 0x00FFFFFFU

4691

#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_SHIFT 0U

4692

#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_WIDTH 24U

4693

#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_259

4694

#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_259__PI_TINIT_F0

4695

4696

#define LPDDR4__DENALI_PI_260_READ_MASK 0x00FFFFFFU

4697

#define LPDDR4__DENALI_PI_260_WRITE_MASK 0x00FFFFFFU

4698

#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_MASK 0x00FFFFFFU

4699

#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_SHIFT 0U

4700

#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_WIDTH 24U

4701

#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_260

4702

#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_260__PI_TINIT3_F0

4703

4704

#define LPDDR4__DENALI_PI_261_READ_MASK 0x00FFFFFFU

4705

#define LPDDR4__DENALI_PI_261_WRITE_MASK 0x00FFFFFFU

4706

#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_MASK 0x00FFFFFFU

4707

#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_SHIFT 0U

4708

#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_WIDTH 24U

4709

#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_261

4710

#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_261__PI_TINIT4_F0

4711

4712

#define LPDDR4__DENALI_PI_262_READ_MASK 0x00FFFFFFU

4713

#define LPDDR4__DENALI_PI_262_WRITE_MASK 0x00FFFFFFU

4714

#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_MASK 0x00FFFFFFU

4715

#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_SHIFT 0U

4716

#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_WIDTH 24U

4717

#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_262

4718

#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_262__PI_TINIT5_F0

4719

4720

#define LPDDR4__DENALI_PI_263_READ_MASK 0x0000FFFFU

4721

#define LPDDR4__DENALI_PI_263_WRITE_MASK 0x0000FFFFU

4722

#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_MASK 0x0000FFFFU

4723

#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_SHIFT 0U

4724

#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_WIDTH 16U

4725

#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_263

4726

#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_263__PI_TXSNR_F0

4727

4728

#define LPDDR4__DENALI_PI_264_READ_MASK 0x00FFFFFFU

4729

#define LPDDR4__DENALI_PI_264_WRITE_MASK 0x00FFFFFFU

4730

#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_MASK 0x00FFFFFFU

4731

#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_SHIFT 0U

4732

#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_WIDTH 24U

4733

#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_264

4734

#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_264__PI_TINIT_F1

4735

4736

#define LPDDR4__DENALI_PI_265_READ_MASK 0x00FFFFFFU

4737

#define LPDDR4__DENALI_PI_265_WRITE_MASK 0x00FFFFFFU

4738

#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_MASK 0x00FFFFFFU

4739

#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_SHIFT 0U

4740

#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_WIDTH 24U

4741

#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_265

4742

#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_265__PI_TINIT3_F1

4743

4744

#define LPDDR4__DENALI_PI_266_READ_MASK 0x00FFFFFFU

4745

#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x00FFFFFFU

4746

#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_MASK 0x00FFFFFFU

4747

#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_SHIFT 0U

4748

#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_WIDTH 24U

4749

#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_266

4750

#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_266__PI_TINIT4_F1

4751

4752

#define LPDDR4__DENALI_PI_267_READ_MASK 0x00FFFFFFU

4753

#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x00FFFFFFU

4754

#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_MASK 0x00FFFFFFU

4755

#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_SHIFT 0U

4756

#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_WIDTH 24U

4757

#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_267

4758

#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_267__PI_TINIT5_F1

4759

4760

#define LPDDR4__DENALI_PI_268_READ_MASK 0x0000FFFFU

4761

#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0000FFFFU

4762

#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_MASK 0x0000FFFFU

4763

#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_SHIFT 0U

4764

#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_WIDTH 16U

4765

#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_268

4766

#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_268__PI_TXSNR_F1

4767

4768

#define LPDDR4__DENALI_PI_269_READ_MASK 0x00FFFFFFU

4769

#define LPDDR4__DENALI_PI_269_WRITE_MASK 0x00FFFFFFU

4770

#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_MASK 0x00FFFFFFU

4771

#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_SHIFT 0U

4772

#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_WIDTH 24U

4773

#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_269

4774

#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_269__PI_TINIT_F2

4775

4776

#define LPDDR4__DENALI_PI_270_READ_MASK 0x00FFFFFFU

4777

#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x00FFFFFFU

4778

#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_MASK 0x00FFFFFFU

4779

#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_SHIFT 0U

4780

#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_WIDTH 24U

4781

#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_270

4782

#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_270__PI_TINIT3_F2

4783

4784

#define LPDDR4__DENALI_PI_271_READ_MASK 0x00FFFFFFU

4785

#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x00FFFFFFU

4786

#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_MASK 0x00FFFFFFU

4787

#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_SHIFT 0U

4788

#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_WIDTH 24U

4789

#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_271

4790

#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_271__PI_TINIT4_F2

4791

4792

#define LPDDR4__DENALI_PI_272_READ_MASK 0x00FFFFFFU

4793

#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x00FFFFFFU

4794

#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_MASK 0x00FFFFFFU

4795

#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_SHIFT 0U

4796

#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_WIDTH 24U

4797

#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_272

4798

#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_272__PI_TINIT5_F2

4799

4800

#define LPDDR4__DENALI_PI_273_READ_MASK 0x0FFFFFFFU

4801

#define LPDDR4__DENALI_PI_273_WRITE_MASK 0x0FFFFFFFU

4802

#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_MASK 0x0000FFFFU

4803

#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_SHIFT 0U

4804

#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_WIDTH 16U

4805

#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_273

4806

#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_273__PI_TXSNR_F2

4807

4808

#define LPDDR4__DENALI_PI_273__PI_RESERVED54_MASK 0x0FFF0000U

4809

#define LPDDR4__DENALI_PI_273__PI_RESERVED54_SHIFT 16U

4810

#define LPDDR4__DENALI_PI_273__PI_RESERVED54_WIDTH 12U

4811

#define LPDDR4__PI_RESERVED54__REG DENALI_PI_273

4812

#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_273__PI_RESERVED54

4813

4814

#define LPDDR4__DENALI_PI_274_READ_MASK 0x0FFF0FFFU

4815

#define LPDDR4__DENALI_PI_274_WRITE_MASK 0x0FFF0FFFU

4816

#define LPDDR4__DENALI_PI_274__PI_RESERVED55_MASK 0x00000FFFU

4817

#define LPDDR4__DENALI_PI_274__PI_RESERVED55_SHIFT 0U

4818

#define LPDDR4__DENALI_PI_274__PI_RESERVED55_WIDTH 12U

4819

#define LPDDR4__PI_RESERVED55__REG DENALI_PI_274

4820

#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_274__PI_RESERVED55

4821

4822

#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_MASK 0x0FFF0000U

4823

#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_SHIFT 16U

4824

#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_WIDTH 12U

4825

#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_274

4826

#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_274__PI_TZQCAL_F0

4827

4828

#define LPDDR4__DENALI_PI_275_READ_MASK 0x000FFF7FU

4829

#define LPDDR4__DENALI_PI_275_WRITE_MASK 0x000FFF7FU

4830

#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_MASK 0x0000007FU

4831

#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_SHIFT 0U

4832

#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_WIDTH 7U

4833

#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_275

4834

#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_275__PI_TZQLAT_F0

4835

4836

#define LPDDR4__DENALI_PI_275__PI_RESERVED56_MASK 0x000FFF00U

4837

#define LPDDR4__DENALI_PI_275__PI_RESERVED56_SHIFT 8U

4838

#define LPDDR4__DENALI_PI_275__PI_RESERVED56_WIDTH 12U

4839

#define LPDDR4__PI_RESERVED56__REG DENALI_PI_275

4840

#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_275__PI_RESERVED56

4841

4842

#define LPDDR4__DENALI_PI_276_READ_MASK 0x0FFF0FFFU

4843

#define LPDDR4__DENALI_PI_276_WRITE_MASK 0x0FFF0FFFU

4844

#define LPDDR4__DENALI_PI_276__PI_RESERVED57_MASK 0x00000FFFU

4845

#define LPDDR4__DENALI_PI_276__PI_RESERVED57_SHIFT 0U

4846

#define LPDDR4__DENALI_PI_276__PI_RESERVED57_WIDTH 12U

4847

#define LPDDR4__PI_RESERVED57__REG DENALI_PI_276

4848

#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_276__PI_RESERVED57

4849

4850

#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_MASK 0x0FFF0000U

4851

#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_SHIFT 16U

4852

#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_WIDTH 12U

4853

#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_276

4854

#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_276__PI_TZQCAL_F1

4855

4856

#define LPDDR4__DENALI_PI_277_READ_MASK 0x000FFF7FU

4857

#define LPDDR4__DENALI_PI_277_WRITE_MASK 0x000FFF7FU

4858

#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_MASK 0x0000007FU

4859

#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_SHIFT 0U

4860

#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_WIDTH 7U

4861

#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_277

4862

#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_277__PI_TZQLAT_F1

4863

4864

#define LPDDR4__DENALI_PI_277__PI_RESERVED58_MASK 0x000FFF00U

4865

#define LPDDR4__DENALI_PI_277__PI_RESERVED58_SHIFT 8U

4866

#define LPDDR4__DENALI_PI_277__PI_RESERVED58_WIDTH 12U

4867

#define LPDDR4__PI_RESERVED58__REG DENALI_PI_277

4868

#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_277__PI_RESERVED58

4869

4870

#define LPDDR4__DENALI_PI_278_READ_MASK 0x0FFF0FFFU

4871

#define LPDDR4__DENALI_PI_278_WRITE_MASK 0x0FFF0FFFU

4872

#define LPDDR4__DENALI_PI_278__PI_RESERVED59_MASK 0x00000FFFU

4873

#define LPDDR4__DENALI_PI_278__PI_RESERVED59_SHIFT 0U

4874

#define LPDDR4__DENALI_PI_278__PI_RESERVED59_WIDTH 12U

4875

#define LPDDR4__PI_RESERVED59__REG DENALI_PI_278

4876

#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_278__PI_RESERVED59

4877

4878

#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_MASK 0x0FFF0000U

4879

#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_SHIFT 16U

4880

#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_WIDTH 12U

4881

#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_278

4882

#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_278__PI_TZQCAL_F2

4883

4884

#define LPDDR4__DENALI_PI_279_READ_MASK 0x000FFF7FU

4885

#define LPDDR4__DENALI_PI_279_WRITE_MASK 0x000FFF7FU

4886

#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_MASK 0x0000007FU

4887

#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_SHIFT 0U

4888

#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_WIDTH 7U

4889

#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_279

4890

#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_279__PI_TZQLAT_F2

4891

4892

#define LPDDR4__DENALI_PI_279__PI_RESERVED60_MASK 0x000FFF00U

4893

#define LPDDR4__DENALI_PI_279__PI_RESERVED60_SHIFT 8U

4894

#define LPDDR4__DENALI_PI_279__PI_RESERVED60_WIDTH 12U

4895

#define LPDDR4__PI_RESERVED60__REG DENALI_PI_279

4896

#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_279__PI_RESERVED60

4897

4898

#define LPDDR4__DENALI_PI_280_READ_MASK 0x0FFF0FFFU

4899

#define LPDDR4__DENALI_PI_280_WRITE_MASK 0x0FFF0FFFU

4900

#define LPDDR4__DENALI_PI_280__PI_RESERVED61_MASK 0x00000FFFU

4901

#define LPDDR4__DENALI_PI_280__PI_RESERVED61_SHIFT 0U

4902

#define LPDDR4__DENALI_PI_280__PI_RESERVED61_WIDTH 12U

4903

#define LPDDR4__PI_RESERVED61__REG DENALI_PI_280

4904

#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_280__PI_RESERVED61

4905

4906

#define LPDDR4__DENALI_PI_280__PI_RESERVED62_MASK 0x0FFF0000U

4907

#define LPDDR4__DENALI_PI_280__PI_RESERVED62_SHIFT 16U

4908

#define LPDDR4__DENALI_PI_280__PI_RESERVED62_WIDTH 12U

4909

#define LPDDR4__PI_RESERVED62__REG DENALI_PI_280

4910

#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_280__PI_RESERVED62

4911

4912

#define LPDDR4__DENALI_PI_281_READ_MASK 0x030F0F0FU

4913

#define LPDDR4__DENALI_PI_281_WRITE_MASK 0x030F0F0FU

4914

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU

4915

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U

4916

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U

4917

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_281

4918

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0

4919

4920

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U

4921

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U

4922

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U

4923

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_281

4924

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1

4925

4926

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U

4927

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U

4928

#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U

4929

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_281

4930

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2

4931

4932

#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_MASK 0x03000000U

4933

#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_SHIFT 24U

4934

#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_WIDTH 2U

4935

#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_281

4936

#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0

4937

4938

#define LPDDR4__DENALI_PI_282_READ_MASK 0x07070303U

4939

#define LPDDR4__DENALI_PI_282_WRITE_MASK 0x07070303U

4940

#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_MASK 0x00000003U

4941

#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_SHIFT 0U

4942

#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_WIDTH 2U

4943

#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_282

4944

#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1

4945

4946

#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_MASK 0x00000300U

4947

#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_SHIFT 8U

4948

#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_WIDTH 2U

4949

#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_282

4950

#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2

4951

4952

#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_MASK 0x00070000U

4953

#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_SHIFT 16U

4954

#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_WIDTH 3U

4955

#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_282

4956

#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0

4957

4958

#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_MASK 0x07000000U

4959

#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_SHIFT 24U

4960

#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_WIDTH 3U

4961

#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_282

4962

#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1

4963

4964

#define LPDDR4__DENALI_PI_283_READ_MASK 0x03030303U

4965

#define LPDDR4__DENALI_PI_283_WRITE_MASK 0x03030303U

4966

#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_MASK 0x00000003U

4967

#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_SHIFT 0U

4968

#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_WIDTH 2U

4969

#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_283

4970

#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0

4971

4972

#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_MASK 0x00000300U

4973

#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_SHIFT 8U

4974

#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_WIDTH 2U

4975

#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_283

4976

#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0

4977

4978

#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_MASK 0x00030000U

4979

#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_SHIFT 16U

4980

#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_WIDTH 2U

4981

#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_283

4982

#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1

4983

4984

#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_MASK 0x03000000U

4985

#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_SHIFT 24U

4986

#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_WIDTH 2U

4987

#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_283

4988

#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1

4989

4990

#define LPDDR4__DENALI_PI_284_READ_MASK 0x7F7F7F7FU

4991

#define LPDDR4__DENALI_PI_284_WRITE_MASK 0x7F7F7F7FU

4992

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_MASK 0x0000007FU

4993

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_SHIFT 0U

4994

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_WIDTH 7U

4995

#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_284

4996

#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0

4997

4998

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_MASK 0x00007F00U

4999

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_SHIFT 8U

5000

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_WIDTH 7U

5001

#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_284

5002

#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1

5003

5004

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_MASK 0x007F0000U

5005

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_SHIFT 16U

5006

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_WIDTH 7U

5007

#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_284

5008

#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0

5009

5010

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_MASK 0x7F000000U

5011

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_SHIFT 24U

5012

#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_WIDTH 7U

5013

#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_284

5014

#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1

5015

5016

#define LPDDR4__DENALI_PI_285_READ_MASK 0x3F3F0303U

5017

#define LPDDR4__DENALI_PI_285_WRITE_MASK 0x3F3F0303U

5018

#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_MASK 0x00000003U

5019

#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_SHIFT 0U

5020

#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_WIDTH 2U

5021

#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_285

5022

#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0

5023

5024

#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_MASK 0x00000300U

5025

#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_SHIFT 8U

5026

#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_WIDTH 2U

5027

#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_285

5028

#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1

5029

5030

#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_MASK 0x003F0000U

5031

#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_SHIFT 16U

5032

#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_WIDTH 6U

5033

#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_285

5034

#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0

5035

5036

#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_MASK 0x3F000000U

5037

#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_SHIFT 24U

5038

#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_WIDTH 6U

5039

#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_285

5040

#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1

5041

5042

#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFF3F3FU

5043

#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFF3F3FU

5044

#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_MASK 0x0000003FU

5045

#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_SHIFT 0U

5046

#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_WIDTH 6U

5047

#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_286

5048

#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0

5049

5050

#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_MASK 0x00003F00U

5051

#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_SHIFT 8U

5052

#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_WIDTH 6U

5053

#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_286

5054

#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1

5055

5056

#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_MASK 0x00FF0000U

5057

#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_SHIFT 16U

5058

#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_WIDTH 8U

5059

#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_286

5060

#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR13_DATA_0

5061

5062

#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_MASK 0xFF000000U

5063

#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_SHIFT 24U

5064

#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_WIDTH 8U

5065

#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_286

5066

#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR15_DATA_0

5067

5068

#define LPDDR4__DENALI_PI_287_READ_MASK 0x00FFFFFFU

5069

#define LPDDR4__DENALI_PI_287_WRITE_MASK 0x00FFFFFFU

5070

#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_MASK 0x000000FFU

5071

#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_SHIFT 0U

5072

#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_WIDTH 8U

5073

#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_287

5074

#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR16_DATA_0

5075

5076

#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_MASK 0x0000FF00U

5077

#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_SHIFT 8U

5078

#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_WIDTH 8U

5079

#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_287

5080

#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR17_DATA_0

5081

5082

#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_MASK 0x00FF0000U

5083

#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_SHIFT 16U

5084

#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_WIDTH 8U

5085

#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_287

5086

#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR20_DATA_0

5087

5088

#define LPDDR4__DENALI_PI_288_READ_MASK 0xFF01FFFFU

5089

#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFF01FFFFU

5090

#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_MASK 0x0001FFFFU

5091

#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_SHIFT 0U

5092

#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_WIDTH 17U

5093

#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_288

5094

#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR32_DATA_0

5095

5096

#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_MASK 0xFF000000U

5097

#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_SHIFT 24U

5098

#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_WIDTH 8U

5099

#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_288

5100

#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR40_DATA_0

5101

5102

#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU

5103

#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU

5104

#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_MASK 0x000000FFU

5105

#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_SHIFT 0U

5106

#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_WIDTH 8U

5107

#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_289

5108

#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR13_DATA_1

5109

5110

#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_MASK 0x0000FF00U

5111

#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_SHIFT 8U

5112

#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_WIDTH 8U

5113

#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_289

5114

#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR15_DATA_1

5115

5116

#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_MASK 0x00FF0000U

5117

#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_SHIFT 16U

5118

#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_WIDTH 8U

5119

#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_289

5120

#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR16_DATA_1

5121

5122

#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_MASK 0xFF000000U

5123

#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_SHIFT 24U

5124

#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_WIDTH 8U

5125

#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_289

5126

#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR17_DATA_1

5127

5128

#define LPDDR4__DENALI_PI_290_READ_MASK 0x01FFFFFFU

5129

#define LPDDR4__DENALI_PI_290_WRITE_MASK 0x01FFFFFFU

5130

#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_MASK 0x000000FFU

5131

#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_SHIFT 0U

5132

#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_WIDTH 8U

5133

#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_290

5134

#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR20_DATA_1

5135

5136

#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_MASK 0x01FFFF00U

5137

#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_SHIFT 8U

5138

#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_WIDTH 17U

5139

#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_290

5140

#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR32_DATA_1

5141

5142

#define LPDDR4__DENALI_PI_291_READ_MASK 0x1F1F1FFFU

5143

#define LPDDR4__DENALI_PI_291_WRITE_MASK 0x1F1F1FFFU

5144

#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_MASK 0x000000FFU

5145

#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_SHIFT 0U

5146

#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_WIDTH 8U

5147

#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_291

5148

#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_291__PI_MR40_DATA_1

5149

5150

#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_MASK 0x00001F00U

5151

#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_SHIFT 8U

5152

#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_WIDTH 5U

5153

#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_291

5154

#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_0

5155

5156

#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_MASK 0x001F0000U

5157

#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_SHIFT 16U

5158

#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_WIDTH 5U

5159

#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_291

5160

#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_1

5161

5162

#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_MASK 0x1F000000U

5163

#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_SHIFT 24U

5164

#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_WIDTH 5U

5165

#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_291

5166

#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CS_MUX_0

5167

5168

#define LPDDR4__DENALI_PI_292_READ_MASK 0x1F1F1F1FU

5169

#define LPDDR4__DENALI_PI_292_WRITE_MASK 0x1F1F1F1FU

5170

#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_MASK 0x0000001FU

5171

#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_SHIFT 0U

5172

#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_WIDTH 5U

5173

#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_292

5174

#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_CS_MUX_1

5175

5176

#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_MASK 0x00001F00U

5177

#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_SHIFT 8U

5178

#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_WIDTH 5U

5179

#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_292

5180

#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_0

5181

5182

#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_MASK 0x001F0000U

5183

#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_SHIFT 16U

5184

#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_WIDTH 5U

5185

#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_292

5186

#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_1

5187

5188

#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_MASK 0x1F000000U

5189

#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_SHIFT 24U

5190

#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_WIDTH 5U

5191

#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_292

5192

#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0

5193

5194

#define LPDDR4__DENALI_PI_293_READ_MASK 0x01FFFF1FU

5195

#define LPDDR4__DENALI_PI_293_WRITE_MASK 0x01FFFF1FU

5196

#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_MASK 0x0000001FU

5197

#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_SHIFT 0U

5198

#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_WIDTH 5U

5199

#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_293

5200

#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1

5201

5202

#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_MASK 0x01FFFF00U

5203

#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_SHIFT 8U

5204

#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_WIDTH 17U

5205

#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_293

5206

#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0

5207

5208

#define LPDDR4__DENALI_PI_294_READ_MASK 0x0301FFFFU

5209

#define LPDDR4__DENALI_PI_294_WRITE_MASK 0x0301FFFFU

5210

#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_MASK 0x0001FFFFU

5211

#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_SHIFT 0U

5212

#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_WIDTH 17U

5213

#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_294

5214

#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1

5215

5216

#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_MASK 0x03000000U

5217

#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_SHIFT 24U

5218

#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_WIDTH 2U

5219

#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_294

5220

#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0

5221

5222

#define LPDDR4__DENALI_PI_295_READ_MASK 0x00030303U

5223

#define LPDDR4__DENALI_PI_295_WRITE_MASK 0x00030303U

5224

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x00000003U

5225

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U

5226

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 2U

5227

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_295

5228

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0

5229

5230

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_MASK 0x00000300U

5231

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_SHIFT 8U

5232

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_WIDTH 2U

5233

#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_295

5234

#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1

5235

5236

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x00030000U

5237

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U

5238

#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 2U

5239

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_295

5240

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1

5241

5242

#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU

5243

#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU

5244

#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU

5245

#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U

5246

#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U

5247

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_296

5248

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0

5249

5250

#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0xFFFF0000U

5251

#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 16U

5252

#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U

5253

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_296

5254

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1

5255

5256

#define LPDDR4__DENALI_PI_297_READ_MASK 0x0001FFFFU

5257

#define LPDDR4__DENALI_PI_297_WRITE_MASK 0x0001FFFFU

5258

#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_MASK 0x0001FFFFU

5259

#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_SHIFT 0U

5260

#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_WIDTH 17U

5261

#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_297

5262

#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0

5263

5264

#define LPDDR4__DENALI_PI_298_READ_MASK 0x0001FFFFU

5265

#define LPDDR4__DENALI_PI_298_WRITE_MASK 0x0001FFFFU

5266

#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_MASK 0x0001FFFFU

5267

#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_SHIFT 0U

5268

#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_WIDTH 17U

5269

#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_298

5270

#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0

5271

5272

#define LPDDR4__DENALI_PI_299_READ_MASK 0x0001FFFFU

5273

#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x0001FFFFU

5274

#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_MASK 0x0001FFFFU

5275

#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_SHIFT 0U

5276

#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_WIDTH 17U

5277

#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_299

5278

#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0

5279

5280

#define LPDDR4__DENALI_PI_300_READ_MASK 0x0001FFFFU

5281

#define LPDDR4__DENALI_PI_300_WRITE_MASK 0x0001FFFFU

5282

#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_MASK 0x0001FFFFU

5283

#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_SHIFT 0U

5284

#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_WIDTH 17U

5285

#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_300

5286

#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0

5287

5288

#define LPDDR4__DENALI_PI_301_READ_MASK 0x0001FFFFU

5289

#define LPDDR4__DENALI_PI_301_WRITE_MASK 0x0001FFFFU

5290

#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_MASK 0x0001FFFFU

5291

#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_SHIFT 0U

5292

#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_WIDTH 17U

5293

#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_301

5294

#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0

5295

5296

#define LPDDR4__DENALI_PI_302_READ_MASK 0x0001FFFFU

5297

#define LPDDR4__DENALI_PI_302_WRITE_MASK 0x0001FFFFU

5298

#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_MASK 0x0001FFFFU

5299

#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_SHIFT 0U

5300

#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_WIDTH 17U

5301

#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_302

5302

#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0

5303

5304

#define LPDDR4__DENALI_PI_303_READ_MASK 0xFF01FFFFU

5305

#define LPDDR4__DENALI_PI_303_WRITE_MASK 0xFF01FFFFU

5306

#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_MASK 0x0001FFFFU

5307

#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_SHIFT 0U

5308

#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_WIDTH 17U

5309

#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_303

5310

#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0

5311

5312

#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_MASK 0xFF000000U

5313

#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_SHIFT 24U

5314

#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_WIDTH 8U

5315

#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_303

5316

#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0

5317

5318

#define LPDDR4__DENALI_PI_304_READ_MASK 0xFFFFFFFFU

5319

#define LPDDR4__DENALI_PI_304_WRITE_MASK 0xFFFFFFFFU

5320

#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_MASK 0x000000FFU

5321

#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_SHIFT 0U

5322

#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_WIDTH 8U

5323

#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_304

5324

#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0

5325

5326

#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_MASK 0x0000FF00U

5327

#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_SHIFT 8U

5328

#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_WIDTH 8U

5329

#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_304

5330

#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0

5331

5332

#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_MASK 0x00FF0000U

5333

#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_SHIFT 16U

5334

#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_WIDTH 8U

5335

#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_304

5336

#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0

5337

5338

#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_MASK 0xFF000000U

5339

#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_SHIFT 24U

5340

#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_WIDTH 8U

5341

#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_304

5342

#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0

5343

5344

#define LPDDR4__DENALI_PI_305_READ_MASK 0x0001FFFFU

5345

#define LPDDR4__DENALI_PI_305_WRITE_MASK 0x0001FFFFU

5346

#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_MASK 0x0001FFFFU

5347

#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_SHIFT 0U

5348

#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_WIDTH 17U

5349

#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_305

5350

#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0

5351

5352

#define LPDDR4__DENALI_PI_306_READ_MASK 0x0001FFFFU

5353

#define LPDDR4__DENALI_PI_306_WRITE_MASK 0x0001FFFFU

5354

#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_MASK 0x0001FFFFU

5355

#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_SHIFT 0U

5356

#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_WIDTH 17U

5357

#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_306

5358

#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0

5359

5360

#define LPDDR4__DENALI_PI_307_READ_MASK 0x0001FFFFU

5361

#define LPDDR4__DENALI_PI_307_WRITE_MASK 0x0001FFFFU

5362

#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_MASK 0x0001FFFFU

5363

#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_SHIFT 0U

5364

#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_WIDTH 17U

5365

#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_307

5366

#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0

5367

5368

#define LPDDR4__DENALI_PI_308_READ_MASK 0x0001FFFFU

5369

#define LPDDR4__DENALI_PI_308_WRITE_MASK 0x0001FFFFU

5370

#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_MASK 0x0001FFFFU

5371

#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_SHIFT 0U

5372

#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_WIDTH 17U

5373

#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_308

5374

#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0

5375

5376

#define LPDDR4__DENALI_PI_309_READ_MASK 0x0001FFFFU

5377

#define LPDDR4__DENALI_PI_309_WRITE_MASK 0x0001FFFFU

5378

#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_MASK 0x0001FFFFU

5379

#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_SHIFT 0U

5380

#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_WIDTH 17U

5381

#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_309

5382

#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0

5383

5384

#define LPDDR4__DENALI_PI_310_READ_MASK 0x0001FFFFU

5385

#define LPDDR4__DENALI_PI_310_WRITE_MASK 0x0001FFFFU

5386

#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_MASK 0x0001FFFFU

5387

#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_SHIFT 0U

5388

#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_WIDTH 17U

5389

#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_310

5390

#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0

5391

5392

#define LPDDR4__DENALI_PI_311_READ_MASK 0xFF01FFFFU

5393

#define LPDDR4__DENALI_PI_311_WRITE_MASK 0xFF01FFFFU

5394

#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_MASK 0x0001FFFFU

5395

#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_SHIFT 0U

5396

#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_WIDTH 17U

5397

#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_311

5398

#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0

5399

5400

#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_MASK 0xFF000000U

5401

#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_SHIFT 24U

5402

#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_WIDTH 8U

5403

#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_311

5404

#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0

5405

5406

#define LPDDR4__DENALI_PI_312_READ_MASK 0xFFFFFFFFU

5407

#define LPDDR4__DENALI_PI_312_WRITE_MASK 0xFFFFFFFFU

5408

#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_MASK 0x000000FFU

5409

#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_SHIFT 0U

5410

#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_WIDTH 8U

5411

#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_312

5412

#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0

5413

5414

#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_MASK 0x0000FF00U

5415

#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_SHIFT 8U

5416

#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_WIDTH 8U

5417

#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_312

5418

#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0

5419

5420

#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_MASK 0x00FF0000U

5421

#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_SHIFT 16U

5422

#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_WIDTH 8U

5423

#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_312

5424

#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0

5425

5426

#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_MASK 0xFF000000U

5427

#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_SHIFT 24U

5428

#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_WIDTH 8U

5429

#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_312

5430

#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0

5431

5432

#define LPDDR4__DENALI_PI_313_READ_MASK 0x0001FFFFU

5433

#define LPDDR4__DENALI_PI_313_WRITE_MASK 0x0001FFFFU

5434

#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_MASK 0x0001FFFFU

5435

#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_SHIFT 0U

5436

#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_WIDTH 17U

5437

#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_313

5438

#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0

5439

5440

#define LPDDR4__DENALI_PI_314_READ_MASK 0x0001FFFFU

5441

#define LPDDR4__DENALI_PI_314_WRITE_MASK 0x0001FFFFU

5442

#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_MASK 0x0001FFFFU

5443

#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_SHIFT 0U

5444

#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_WIDTH 17U

5445

#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_314

5446

#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0

5447

5448

#define LPDDR4__DENALI_PI_315_READ_MASK 0x0001FFFFU

5449

#define LPDDR4__DENALI_PI_315_WRITE_MASK 0x0001FFFFU

5450

#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_MASK 0x0001FFFFU

5451

#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_SHIFT 0U

5452

#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_WIDTH 17U

5453

#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_315

5454

#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0

5455

5456

#define LPDDR4__DENALI_PI_316_READ_MASK 0x0001FFFFU

5457

#define LPDDR4__DENALI_PI_316_WRITE_MASK 0x0001FFFFU

5458

#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_MASK 0x0001FFFFU

5459

#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_SHIFT 0U

5460

#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_WIDTH 17U

5461

#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_316

5462

#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0

5463

5464

#define LPDDR4__DENALI_PI_317_READ_MASK 0x0001FFFFU

5465

#define LPDDR4__DENALI_PI_317_WRITE_MASK 0x0001FFFFU

5466

#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_MASK 0x0001FFFFU

5467

#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_SHIFT 0U

5468

#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_WIDTH 17U

5469

#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_317

5470

#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0

5471

5472

#define LPDDR4__DENALI_PI_318_READ_MASK 0x0001FFFFU

5473

#define LPDDR4__DENALI_PI_318_WRITE_MASK 0x0001FFFFU

5474

#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_MASK 0x0001FFFFU

5475

#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_SHIFT 0U

5476

#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_WIDTH 17U

5477

#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_318

5478

#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0

5479

5480

#define LPDDR4__DENALI_PI_319_READ_MASK 0xFF01FFFFU

5481

#define LPDDR4__DENALI_PI_319_WRITE_MASK 0xFF01FFFFU

5482

#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_MASK 0x0001FFFFU

5483

#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_SHIFT 0U

5484

#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_WIDTH 17U

5485

#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_319

5486

#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0

5487

5488

#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_MASK 0xFF000000U

5489

#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_SHIFT 24U

5490

#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_WIDTH 8U

5491

#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_319

5492

#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0

5493

5494

#define LPDDR4__DENALI_PI_320_READ_MASK 0xFFFFFFFFU

5495

#define LPDDR4__DENALI_PI_320_WRITE_MASK 0xFFFFFFFFU

5496

#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_MASK 0x000000FFU

5497

#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_SHIFT 0U

5498

#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_WIDTH 8U

5499

#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_320

5500

#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0

5501

5502

#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_MASK 0x0000FF00U

5503

#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_SHIFT 8U

5504

#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_WIDTH 8U

5505

#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_320

5506

#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0

5507

5508

#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_MASK 0x00FF0000U

5509

#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_SHIFT 16U

5510

#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_WIDTH 8U

5511

#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_320

5512

#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0

5513

5514

#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_MASK 0xFF000000U

5515

#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_SHIFT 24U

5516

#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_WIDTH 8U

5517

#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_320

5518

#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0

5519

5520

#define LPDDR4__DENALI_PI_321_READ_MASK 0x0001FFFFU

5521

#define LPDDR4__DENALI_PI_321_WRITE_MASK 0x0001FFFFU

5522

#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_MASK 0x0001FFFFU

5523

#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_SHIFT 0U

5524

#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_WIDTH 17U

5525

#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_321

5526

#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1

5527

5528

#define LPDDR4__DENALI_PI_322_READ_MASK 0x0001FFFFU

5529

#define LPDDR4__DENALI_PI_322_WRITE_MASK 0x0001FFFFU

5530

#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_MASK 0x0001FFFFU

5531

#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_SHIFT 0U

5532

#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_WIDTH 17U

5533

#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_322

5534

#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1

5535

5536

#define LPDDR4__DENALI_PI_323_READ_MASK 0x0001FFFFU

5537

#define LPDDR4__DENALI_PI_323_WRITE_MASK 0x0001FFFFU

5538

#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_MASK 0x0001FFFFU

5539

#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_SHIFT 0U

5540

#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_WIDTH 17U

5541

#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_323

5542

#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1

5543

5544

#define LPDDR4__DENALI_PI_324_READ_MASK 0x0001FFFFU

5545

#define LPDDR4__DENALI_PI_324_WRITE_MASK 0x0001FFFFU

5546

#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_MASK 0x0001FFFFU

5547

#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_SHIFT 0U

5548

#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_WIDTH 17U

5549

#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_324

5550

#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1

5551

5552

#define LPDDR4__DENALI_PI_325_READ_MASK 0x0001FFFFU

5553

#define LPDDR4__DENALI_PI_325_WRITE_MASK 0x0001FFFFU

5554

#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_MASK 0x0001FFFFU

5555

#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_SHIFT 0U

5556

#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_WIDTH 17U

5557

#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_325

5558

#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1

5559

5560

#define LPDDR4__DENALI_PI_326_READ_MASK 0x0001FFFFU

5561

#define LPDDR4__DENALI_PI_326_WRITE_MASK 0x0001FFFFU

5562

#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_MASK 0x0001FFFFU

5563

#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_SHIFT 0U

5564

#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_WIDTH 17U

5565

#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_326

5566

#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1

5567

5568

#define LPDDR4__DENALI_PI_327_READ_MASK 0xFF01FFFFU

5569

#define LPDDR4__DENALI_PI_327_WRITE_MASK 0xFF01FFFFU

5570

#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_MASK 0x0001FFFFU

5571

#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_SHIFT 0U

5572

#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_WIDTH 17U

5573

#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_327

5574

#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1

5575

5576

#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_MASK 0xFF000000U

5577

#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_SHIFT 24U

5578

#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_WIDTH 8U

5579

#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_327

5580

#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1

5581

5582

#define LPDDR4__DENALI_PI_328_READ_MASK 0xFFFFFFFFU

5583

#define LPDDR4__DENALI_PI_328_WRITE_MASK 0xFFFFFFFFU

5584

#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_MASK 0x000000FFU

5585

#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_SHIFT 0U

5586

#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_WIDTH 8U

5587

#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_328

5588

#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1

5589

5590

#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_MASK 0x0000FF00U

5591

#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_SHIFT 8U

5592

#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_WIDTH 8U

5593

#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_328

5594

#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1

5595

5596

#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_MASK 0x00FF0000U

5597

#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_SHIFT 16U

5598

#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_WIDTH 8U

5599

#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_328

5600

#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1

5601

5602

#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_MASK 0xFF000000U

5603

#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_SHIFT 24U

5604

#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_WIDTH 8U

5605

#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_328

5606

#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1

5607

5608

#define LPDDR4__DENALI_PI_329_READ_MASK 0x0001FFFFU

5609

#define LPDDR4__DENALI_PI_329_WRITE_MASK 0x0001FFFFU

5610

#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_MASK 0x0001FFFFU

5611

#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_SHIFT 0U

5612

#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_WIDTH 17U

5613

#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_329

5614

#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1

5615

5616

#define LPDDR4__DENALI_PI_330_READ_MASK 0x0001FFFFU

5617

#define LPDDR4__DENALI_PI_330_WRITE_MASK 0x0001FFFFU

5618

#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_MASK 0x0001FFFFU

5619

#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_SHIFT 0U

5620

#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_WIDTH 17U

5621

#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_330

5622

#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1

5623

5624

#define LPDDR4__DENALI_PI_331_READ_MASK 0x0001FFFFU

5625

#define LPDDR4__DENALI_PI_331_WRITE_MASK 0x0001FFFFU

5626

#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_MASK 0x0001FFFFU

5627

#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_SHIFT 0U

5628

#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_WIDTH 17U

5629

#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_331

5630

#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1

5631

5632

#define LPDDR4__DENALI_PI_332_READ_MASK 0x0001FFFFU

5633

#define LPDDR4__DENALI_PI_332_WRITE_MASK 0x0001FFFFU

5634

#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_MASK 0x0001FFFFU

5635

#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_SHIFT 0U

5636

#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_WIDTH 17U

5637

#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_332

5638

#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1

5639

5640

#define LPDDR4__DENALI_PI_333_READ_MASK 0x0001FFFFU

5641

#define LPDDR4__DENALI_PI_333_WRITE_MASK 0x0001FFFFU

5642

#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_MASK 0x0001FFFFU

5643

#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_SHIFT 0U

5644

#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_WIDTH 17U

5645

#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_333

5646

#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1

5647

5648

#define LPDDR4__DENALI_PI_334_READ_MASK 0x0001FFFFU

5649

#define LPDDR4__DENALI_PI_334_WRITE_MASK 0x0001FFFFU

5650

#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_MASK 0x0001FFFFU

5651

#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_SHIFT 0U

5652

#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_WIDTH 17U

5653

#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_334

5654

#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1

5655

5656

#define LPDDR4__DENALI_PI_335_READ_MASK 0xFF01FFFFU

5657

#define LPDDR4__DENALI_PI_335_WRITE_MASK 0xFF01FFFFU

5658

#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_MASK 0x0001FFFFU

5659

#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_SHIFT 0U

5660

#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_WIDTH 17U

5661

#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_335

5662

#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1

5663

5664

#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_MASK 0xFF000000U

5665

#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_SHIFT 24U

5666

#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_WIDTH 8U

5667

#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_335

5668

#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1

5669

5670

#define LPDDR4__DENALI_PI_336_READ_MASK 0xFFFFFFFFU

5671

#define LPDDR4__DENALI_PI_336_WRITE_MASK 0xFFFFFFFFU

5672

#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_MASK 0x000000FFU

5673

#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_SHIFT 0U

5674

#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_WIDTH 8U

5675

#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_336

5676

#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1

5677

5678

#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_MASK 0x0000FF00U

5679

#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_SHIFT 8U

5680

#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_WIDTH 8U

5681

#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_336

5682

#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1

5683

5684

#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_MASK 0x00FF0000U

5685

#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_SHIFT 16U

5686

#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_WIDTH 8U

5687

#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_336

5688

#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1

5689

5690

#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_MASK 0xFF000000U

5691

#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_SHIFT 24U

5692

#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_WIDTH 8U

5693

#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_336

5694

#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1

5695

5696

#define LPDDR4__DENALI_PI_337_READ_MASK 0x0001FFFFU

5697

#define LPDDR4__DENALI_PI_337_WRITE_MASK 0x0001FFFFU

5698

#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_MASK 0x0001FFFFU

5699

#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_SHIFT 0U

5700

#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_WIDTH 17U

5701

#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_337

5702

#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1

5703

5704

#define LPDDR4__DENALI_PI_338_READ_MASK 0x0001FFFFU

5705

#define LPDDR4__DENALI_PI_338_WRITE_MASK 0x0001FFFFU

5706

#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_MASK 0x0001FFFFU

5707

#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_SHIFT 0U

5708

#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_WIDTH 17U

5709

#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_338

5710

#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1

5711

5712

#define LPDDR4__DENALI_PI_339_READ_MASK 0x0001FFFFU

5713

#define LPDDR4__DENALI_PI_339_WRITE_MASK 0x0001FFFFU

5714

#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_MASK 0x0001FFFFU

5715

#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_SHIFT 0U

5716

#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_WIDTH 17U

5717

#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_339

5718

#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1

5719

5720

#define LPDDR4__DENALI_PI_340_READ_MASK 0x0001FFFFU

5721

#define LPDDR4__DENALI_PI_340_WRITE_MASK 0x0001FFFFU

5722

#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_MASK 0x0001FFFFU

5723

#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_SHIFT 0U

5724

#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_WIDTH 17U

5725

#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_340

5726

#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1

5727

5728

#define LPDDR4__DENALI_PI_341_READ_MASK 0x0001FFFFU

5729

#define LPDDR4__DENALI_PI_341_WRITE_MASK 0x0001FFFFU

5730

#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_MASK 0x0001FFFFU

5731

#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_SHIFT 0U

5732

#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_WIDTH 17U

5733

#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_341

5734

#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1

5735

5736

#define LPDDR4__DENALI_PI_342_READ_MASK 0x0001FFFFU

5737

#define LPDDR4__DENALI_PI_342_WRITE_MASK 0x0001FFFFU

5738

#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_MASK 0x0001FFFFU

5739

#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_SHIFT 0U

5740

#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_WIDTH 17U

5741

#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_342

5742

#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1

5743

5744

#define LPDDR4__DENALI_PI_343_READ_MASK 0xFF01FFFFU

5745

#define LPDDR4__DENALI_PI_343_WRITE_MASK 0xFF01FFFFU

5746

#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_MASK 0x0001FFFFU

5747

#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_SHIFT 0U

5748

#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_WIDTH 17U

5749

#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_343

5750

#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1

5751

5752

#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_MASK 0xFF000000U

5753

#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_SHIFT 24U

5754

#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_WIDTH 8U

5755

#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_343

5756

#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1

5757

5758

#define LPDDR4__DENALI_PI_344_READ_MASK 0xFFFFFFFFU

5759

#define LPDDR4__DENALI_PI_344_WRITE_MASK 0xFFFFFFFFU

5760

#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_MASK 0x000000FFU

5761

#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_SHIFT 0U

5762

#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_WIDTH 8U

5763

#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_344

5764

#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1

5765

5766

#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_MASK 0x0000FF00U

5767

#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_SHIFT 8U

5768

#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_WIDTH 8U

5769

#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_344

5770

#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1

5771

5772

#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_MASK 0x00FF0000U

5773

#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_SHIFT 16U

5774

#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_WIDTH 8U

5775

#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_344

5776

#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1

5777

5778

#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_MASK 0xFF000000U

5779

#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_SHIFT 24U

5780

#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_WIDTH 8U

5781

#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_344

5782

#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1

5783

5784

#endif /* REG_LPDDR4_PI_MACROS_H_ */